Necessity of clk'event in Process

[Lord_MiL]

Hey all!
I'm a long time reader but first time poster here on the VHDL boards. A question arose recently in a class of mine about why one must do the following:

PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN -- or rising_edge(clk)

as opposed to just writing:

PROCESS (clk)
BEGIN
IF (clk='1') THEN

Many students argued that the second snippet of code would work perfectly fine as clk'EVENT is implied by clk being in the PROCESS' sensitivity list. The professor said that he didn't know why clk'EVENT is necessary but he's pretty sure that it is. When I first started studying VHDL, I read several books and I swear I remember reading that the sensitivity list of a process is used explicity in simulation but that in synthesis it is more of a hint to the compiler and that the second code example will not infer the correct memory devices. Unfortunately, however, I no longer have access to my VHDL book. :argh:

Several students in the class insisted that they always write their code in the second format above and that it always "works just fine." However, when I asked if they just simulated this code or if they actually synthesized and then simulated or verified the actual synthesis they insisted there wasn't any difference. :hmm2:

Anyway, I always write my code in the first style but I hate having unanswered questions in my head so I was hoping someone could clear this matter up for me. Thanks!

 

[Lord_MiL]

Just wanted to post back in case anyone has this question in the future:

I did eventually find a few references in VHDL text books to what I was asking about and sure enough, I was right. While code that simply puts the clock in a PROCESS' sensitivity list in order to indicate a clock edge may in fact simulate correctly, the compiler will not produce the correct circuit.

I still wish I could find a mention of this in the standard or something so that my answer had a little more authority but at least I found mention of it somewhere.