Need HELP array !

[Hayami]

Hi all,

when compiling code with xilinx ISE i get this error code:
WARNING:Xst:790 - C:/Programmi/bios/bios.vhd line 51 and 53: Index
value(s) does not match array range, simulation mismatch.

I spend last 3 days to find the bug without any results, please help!
The code read out one byte each clock edge from the array.

Thank you very much



entity ram_module is
port(clk : in std_logic;
R_W : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0));

end ram_module;


architecture BHV of ram_module is

signal addr: std_logic_vector(3 downto 0);
type memory is array (0 to 9) of std_logic_vector(15 downto 0);

signal reg : memory := (


"1110001100000000",
"0101010010100000",
"0001010010101100",
"0000010000001010",
"0110100001000000",
"0001011011000100",
"0001001001100001",
"0001010010111111",
"0000111000000100",
"1111111111111111" --HALT

);

begin
process(clk, R_W)
begin

if (clk = '1' and clk' event) then
if (R_W = '1') then
data_out <= reg(conv_integer(addr)); -- LINE 51
else
reg(conv_integer(addr)) <= data_in; -- LINE 53
end if;

addr<=addr+1;
end if;

end process;
end BHV;

 

[Oleg]

Hi all,

when compiling code with xilinx ISE i get this error code:
WARNING:Xst:790 - C:/Programmi/bios/bios.vhd line 51 and 53: Index
value(s) does not match array range, simulation mismatch.

I spend last 3 days to find the bug without any results, please help!
The code read out one byte each clock edge from the array.

Thank you very much



entity ram_module is
port(clk : in std_logic;
R_W : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0));

end ram_module;


architecture BHV of ram_module is

signal addr: std_logic_vector(3 downto 0);
type memory is array (0 to 9) of std_logic_vector(15 downto 0);

signal reg : memory := (


"1110001100000000",
"0101010010100000",
"0001010010101100",
"0000010000001010",
"0110100001000000",
"0001011011000100",
"0001001001100001",
"0001010010111111",
"0000111000000100",
"1111111111111111" --HALT

);

begin
process(clk, R_W)
begin

if (clk = '1' and clk' event) then
if (R_W = '1') then
data_out <= reg(conv_integer(addr)); -- LINE 51
else
reg(conv_integer(addr)) <= data_in; -- LINE 53
end if;

addr<=addr+1;
end if;

end process;
end BHV;

Hi,
The error message that u get is totaly normal :

1-your addr signal size is 4 bits "signal addr: std_logic_vector(3
downto 0)"; with allow you to address 16 positions but the reg signal
is only "(0 to 9)" whitch is 10 positions. So its normal that u have
index value does note match array size when the tool wil tray to index
your reg signal with 11 for exemple.

2- your signal addr is never inisialized that will cause it to stay
all time in "UUUU" during the simulation (because U+1=U :
"addr<=addr+1;")

Good luck.

 

[Egbert Molenkamp]

Hi all,

when compiling code with xilinx ISE i get this error code:
WARNING:Xst:790 - C:/Programmi/bios/bios.vhd line 51 and 53: Index
value(s) does not match array range, simulation mismatch.

signal addr: std_logic_vector(3 downto 0);
type memory is array (0 to 9) of std_logic_vector(15 downto 0); ;

addr<=addr+1;

The array index is from 0 to 9.
If you perform a simulation and addr is 9, and you add 1 to it you will get
an error.
Synthesis will (probably) use 4 bits and will go to 10 (a mismatch)

Probably you need the behaviour:
addr <= (addr + 1) mod 10

However synthesis can not handle this. Work around replace line with
if addr <9 then
addr <= addr+1;
else
addr <= 0;
end if;

Egbert Molenkamp

 

[deep]

i wonder if conv_integer function works in Xilinx synthesis...

dk

 

[Ray Andraka]

Yes, conv_integer works under XST, however use ieee.numeric_std
instead. In that case, the function is to_integer.

i wonder if conv_integer function works in Xilinx synthesis...

dk

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President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
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