Need Help for Qaurtus tool

Discussion in 'VHDL' started by Mary, Aug 31, 2006.

  1. Mary

    Mary Guest

    Hai........

    Im designing a uart with Quartus. Is it possible to design the
    the whole design, simulate and synthesis using Quartus..Can anyone help
    me the steps to be done for the programming... The tools avaible with
    me are only Modelsim and Quartus

    Mary
    Mary, Aug 31, 2006
    #1
    1. Advertising

  2. Mary

    KJ Guest

    "Mary" <> wrote in message
    news:...
    > Im designing a uart with Quartus. Is it possible to design the
    > the whole design, simulate and synthesis using Quartus..

    Yes

    > Can anyone help
    > me the steps to be done for the programming...

    If you have a specific question, ask it. As a general guide, consult the
    Quartus documentation.

    > The tools avaible with
    > me are only Modelsim and Quartus

    Good choices, they will do the job.

    KJ
    KJ, Aug 31, 2006
    #2
    1. Advertising

  3. Mary

    Mary Guest

    Hi......
    I've written the code for uart...... While i did the functional
    simulation , everything came out well. But after doing the timing
    simulation some of the signals ( for example shift_reg( 11 dwonto 0))
    reduced to shift_reg (9 downto 0) in the waveform file........In the
    simulation report it was said tat ignored node in vector source
    file....
    The data bits is of 8 bit wide and after adding the start , parity and
    stop bit, it becomes 12 bit........ this is how i did it .......

    if shift='1' then
    if status_reg(1)='1' and status_reg(0)='0' then
    if count=0 then
    txshift_reg(0)<='0'; -- load start
    bit
    txshift_reg(8 downto 1)<= buffer_reg; -- load data to
    transmit_shift reg
    txshift_reg(9)<=status_reg(2); -- load parity bit
    txshift_reg(11 downto 10)<="11";
    status_reg(1)<='0'; -- change the
    status of shift register
    status_reg(0)<='1'; -- change the
    status of buffer register

    In fuctional simulation it dint showed any error..... but it didnt give
    the expected output for timing simution.. wat are the steps v have to
    take before doing the timing simultion.

    KJ wrote:

    > "Mary" <> wrote in message
    > news:...
    > > Im designing a uart with Quartus. Is it possible to design the
    > > the whole design, simulate and synthesis using Quartus..

    > Yes
    >
    > > Can anyone help
    > > me the steps to be done for the programming...

    > If you have a specific question, ask it. As a general guide, consult the
    > Quartus documentation.
    >
    > > The tools avaible with
    > > me are only Modelsim and Quartus

    > Good choices, they will do the job.
    >
    > KJ
    Mary, Sep 8, 2006
    #3
  4. Mary wrote:
    > Hi......
    > I've written the code for uart...... While i did the functional
    > simulation , everything came out well. But after doing the timing
    > simulation some of the signals ( for example shift_reg( 11 dwonto 0))
    > reduced to shift_reg (9 downto 0)


    Synthesis is clever, and often matches my code with
    fewer register than I expect.
    This alone is not a problem.

    > In fuctional simulation it dint showed any error..... but it didnt give
    > the expected output for timing simution.. wat are the steps v have to
    > take before doing the timing simultion.


    With the right design rules, this should never happen.
    I would guess that you either have
    a combinational race or that you
    used an AFTER clause to create a delay.

    Check the reference design here:

    http://home.comcast.net/~mike_treseler/

    for a uart code example that works fine with quartus and modelsim.

    -- Mike Treseler
    Mike Treseler, Sep 8, 2006
    #4
  5. Mary

    Mary Guest

    Thank u Mike for ur reply... Can u explain the combinational race
    condition . how it occurs and how to avoid it.
    Mary, Sep 11, 2006
    #5
  6. Mary wrote:
    > Thank u Mike for ur reply... Can u explain the combinational race
    > condition . how it occurs


    If I change the asynch input (a),
    port b might follow the new value
    while c or d follow the old value
    because of wire and gate delay:

    clk>-
    a >--o--[dq]-------------------------> b
    \---------------[dq]-----------> c
    \
    o----------------------[dq]--> d

    > how to avoid it.


    Synchronize all inputs and
    use a synchronous template
    to describe outputs.
    I like this one:

    http://home.comcast.net/~mike_treseler/sync_template.vhd

    -- Mike Treseler
    Mike Treseler, Oct 2, 2006
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. msnews.microsoft.com
    Replies:
    0
    Views:
    2,306
    msnews.microsoft.com
    Jun 26, 2003
  2. Learner
    Replies:
    3
    Views:
    3,865
    venkatmath
    Jul 12, 2008
  3. Jed
    Replies:
    28
    Views:
    656
    Michael O'Keeffe
    Oct 16, 2005
  4. Replies:
    8
    Views:
    352
    Martin Gregorie
    Jun 26, 2007
  5. Learner
    Replies:
    10
    Views:
    399
    Dominick Baier [DevelopMentor]
    Mar 7, 2006
Loading...

Share This Page