Need Help for Qaurtus tool

[Mary]

Hai........

Im designing a uart with Quartus. Is it possible to design the
the whole design, simulate and synthesis using Quartus..Can anyone help
me the steps to be done for the programming... The tools avaible with
me are only Modelsim and Quartus

Mary

 

[KJ]

Im designing a uart with Quartus. Is it possible to design the
the whole design, simulate and synthesis using Quartus.. Yes

Can anyone help
me the steps to be done for the programming...

If you have a specific question, ask it. As a general guide, consult the
Quartus documentation.

The tools avaible with
me are only Modelsim and Quartus

Good choices, they will do the job.

KJ

 

[Mary]

Hi......
I've written the code for uart...... While i did the functional
simulation , everything came out well. But after doing the timing
simulation some of the signals ( for example shift_reg( 11 dwonto 0))
reduced to shift_reg (9 downto 0) in the waveform file........In the
simulation report it was said tat ignored node in vector source
file....
The data bits is of 8 bit wide and after adding the start , parity and
stop bit, it becomes 12 bit........ this is how i did it .......

if shift='1' then
if status_reg(1)='1' and status_reg(0)='0' then
if count=0 then
txshift_reg(0)<='0'; -- load start
bit
txshift_reg(8 downto 1)<= buffer_reg; -- load data to
transmit_shift reg
txshift_reg(9)<=status_reg(2); -- load parity bit
txshift_reg(11 downto 10)<="11";
status_reg(1)<='0'; -- change the
status of shift register
status_reg(0)<='1'; -- change the
status of buffer register

In fuctional simulation it dint showed any error..... but it didnt give
the expected output for timing simution.. wat are the steps v have to
take before doing the timing simultion.

 

[Mike Treseler]

Hi......
I've written the code for uart...... While i did the functional
simulation , everything came out well. But after doing the timing
simulation some of the signals ( for example shift_reg( 11 dwonto 0))
reduced to shift_reg (9 downto 0)

Synthesis is clever, and often matches my code with
fewer register than I expect.
This alone is not a problem.

In fuctional simulation it dint showed any error..... but it didnt give
the expected output for timing simution.. wat are the steps v have to
take before doing the timing simultion.

With the right design rules, this should never happen.
I would guess that you either have
a combinational race or that you
used an AFTER clause to create a delay.

Check the reference design here:

http://home.comcast.net/~mike_treseler/

for a uart code example that works fine with quartus and modelsim.

-- Mike Treseler

 

[Mary]

Thank u Mike for ur reply... Can u explain the combinational race
condition . how it occurs and how to avoid it.

 

[Mike Treseler]

Thank u Mike for ur reply... Can u explain the combinational race
condition . how it occurs

If I change the asynch input (a),
port b might follow the new value
while c or d follow the old value
because of wire and gate delay:

clk>-
a >--o--[dq]-------------------------> b
\---------------[dq]-----------> c
\
o----------------------[dq]--> d

how to avoid it.

Synchronize all inputs and
use a synchronous template
to describe outputs.
I like this one:

http://home.comcast.net/~mike_treseler/sync_template.vhd

-- Mike Treseler