need help in designing normalization

Discussion in 'VHDL' started by ledinhkha@gmail.com, Dec 10, 2005.

  1. Guest

    hi,
    i'm new in VHDL, and i'm taking a class about VLSI. My task is to
    design a chip that receiving a set of numbers (in serial), then finding
    the max and min of the input set and normalize it to the range [0;255].
    I've also tried to do in VHDL with Xilinx, and I have a problem with
    the divide operator (because i have to divide by my max value). Some
    people tell me that we just can divide by a number that is in the form
    power of 2 (ex: 1024, 512, ...).
    Is there anyone that have ever done sth similar to me? if yes then pls
    advice me.
    Thks
    Kha
     
    , Dec 10, 2005
    #1
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  2. Guest

    schrieb:

    > hi,
    > i'm new in VHDL, and i'm taking a class about VLSI. My task is to
    > design a chip that receiving a set of numbers (in serial), then finding
    > the max and min of the input set and normalize it to the range [0;255].
    > I've also tried to do in VHDL with Xilinx, and I have a problem with
    > the divide operator (because i have to divide by my max value). Some
    > people tell me that we just can divide by a number that is in the form
    > power of 2 (ex: 1024, 512, ...).


    Thats wrong, you could easy divide by 2^n by shifting, while dividing
    by integer is a bit harder in digital devices. I would recommend you
    start with simple designs for learning vhdl before doing that task
    above.
    Dividing is often done serial because of area and timing constraints,
    search serial dividers (or parallel dividers) for more.

    bye Thomas
     
    , Dec 12, 2005
    #2
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  3. Guest

    thks so much, Thomas. I will try by some simple designs, and finding
    about serial dividers to read.
    Have a nice day!
    Kha
     
    , Dec 12, 2005
    #3
  4. Ray Andraka Guest

    wrote:
    > hi,
    > i'm new in VHDL, and i'm taking a class about VLSI. My task is to
    > design a chip that receiving a set of numbers (in serial), then finding
    > the max and min of the input set and normalize it to the range [0;255].
    > I've also tried to do in VHDL with Xilinx, and I have a problem with
    > the divide operator (because i have to divide by my max value). Some
    > people tell me that we just can divide by a number that is in the form
    > power of 2 (ex: 1024, 512, ...).
    > Is there anyone that have ever done sth similar to me? if yes then pls
    > advice me.
    > Thks
    > Kha
    >


    You'll need a buffer to hold the samples while you find the min and max.
    You didn't mention how many bits your input data is.

    Division can be done as a multiplication by the reciprocal of the
    divisor, in which case the reciprocal can come from a look-up table in
    block RAM. For larger numbers of bits, this obviously gets cumbersome.
    You can improve the range by using the upper bits of the divisor to
    address a reciprocal, and then the lower bits to address an
    interpolation slope table, and use that to do a linear interpolation to
    get a more precise answer. That provides a fairly compact, and one of
    the fastest ways to do a 16 bit divide in an FPGA. If you need more
    precision, look up array divider or restoring or non-restoring division.
     
    Ray Andraka, Sep 6, 2006
    #4
  5. KJ Guest

    > Division can be done as a multiplication by the reciprocal of the
    > divisor, in which case the reciprocal can come from a look-up table in
    > block RAM. For larger numbers of bits, this obviously gets cumbersome.


    You can also divide by simply using the lpm_divide function that is
    part of the EIA standard LPM package.

    KJ
     
    KJ, Sep 6, 2006
    #5
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