need help in VHDL FIR filter very urgent

Discussion in 'VHDL' started by erick232, Jun 26, 2010.

  1. erick232

    erick232

    Joined:
    Jun 26, 2010
    Messages:
    5
    I have attached my file and my VHDL code about FIR filter..! please, help me..

    could u please tell me how to drive the sel statement..!
     

    Attached Files:

    erick232, Jun 26, 2010
    #1
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  2. erick232

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Hi Erick

    Try to study this page about multiplexers.
    (copy to the browser) jjmk.dk/MMMI/VHDL/Kompendie/Mux/mux_example.htm

    At this page will you find some other examples about FIR filters.
    jjmk.dk/MMMI/Lessons/10_Filters/Parallel_FIR/parallel_fir.htm
     
    jeppe, Jun 27, 2010
    #2
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  3. erick232

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Hi erics

    I had some sparetime :)
    Seems the driver for Sel should be part of the statemachine - try this

    Code:
    entity DataPath2 is
        port ( f,c:in std_logic_vector(15 downto 0);
            clk, reset: in std_logic;
            oe : out bit;
            result:out std_logic_vector(15 downto 0));
    end DataPath2;
    
    architecture Behavioral of DataPath2 is
         signal  s2,s3: std_logic_vector(15 downto 0):=(others=>'0');
         type state_type is(st0,st1,st2,st3,st4,st5);
         signal pres_state,next_state :state_type;
         signal temp_reg,ts2,ts3 : std_logic_vector(18 downto 0):=(others=>'0');
         signal sel :bit;
    begin
    
       datapath:process (pres_state,s2,s3,f,c)
          variable reg : std_logic_vector (31 downto 0):=(others=>'0');
       begin
         reg :=f*c;
         s2 <= reg (31 downto 16);
         next_state<= pres_state;
         oe <= '0';  -- Default value for oe
         sel <= '1'; -- Default value for sel
         case pres_state is
             when st0 =>
                  sel <= '0';  -- new value for sel
                  next_state <= st1;
             when st1 =>
                  next_state <= st2;
             when st2 =>
                   next_state <= st3;
              when st3 =>
                   next_state <= st4;
              when st4 =>
                   next_state <= st5;
              when st5 =>
                   oe <='1';  -- new value for oe 
                   next_state <= st0;
             end case;
         end process;
    
       ts2      <= "000"& s2;
       ts3      <= "000"& s3;
       temp_reg <= ts2 + ts3;
       result   <= s3;
    
         process (clk,reset)
           begin
            if (reset='1') then
               pres_state <= st0;
               s3        <= (others =>'0');
            elsif (rising_edge (clk))then
               if sel='0' then
                  s3 <= s2; 
               else 
                  s3 <= temp_reg(18 downto 3);        
               end if; 
               pres_state <= next_state;
            end if;
         end process;
    end Behavioral;
     
    jeppe, Jun 29, 2010
    #3
  4. erick232

    erick232

    Joined:
    Jun 26, 2010
    Messages:
    5
    tack so mycket.! jeppe , for your valuable idea.
     
    erick232, Jul 1, 2010
    #4
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