Need help to tranlate ABEL

[Steven P]

I have following ABEL program to be translated to VHDL:

!IOWR pin;
BOOT pin istype "reg_d";


BOOT.clk = !IOWR;
BOOT.aset = RESET;
BOOT.aclr = 0;
BOOT.d = IOD0 & BOOT_BASE # (BOOT.pin & !BOOT_BASE);
BOOT.oe = 1;

My VHDL looks like:

process( RESET, IOWR)

begin
if (RESET = '0') then
BOOT_tmp <= '0';
elsif( falling_edge(IOWR)) then
BOOT_tmp <= (IOD0 and BOOT_BASE ) or (BOOT_tmp and ( not
BOOT_BASE));
end if;
end process;

BOOT <= BOOT_tmp;


Is it correct? Is BOOT.oe = 1 means boot is tri-state ?

Any help will be very appreciated!

Steven

 

[Dave Higton]

In message <[email protected]>

I have following ABEL program to be translated to VHDL:

!IOWR pin;
BOOT pin istype "reg_d";


BOOT.clk = !IOWR;
BOOT.aset = RESET;
BOOT.aclr = 0;
BOOT.d = IOD0 & BOOT_BASE # (BOOT.pin & !BOOT_BASE);
BOOT.oe = 1;

My VHDL looks like:

process( RESET, IOWR)

begin
if (RESET = '0') then
BOOT_tmp <= '0';
elsif( falling_edge(IOWR)) then
BOOT_tmp <= (IOD0 and BOOT_BASE ) or (BOOT_tmp and ( not
BOOT_BASE));
end if;
end process;

BOOT <= BOOT_tmp;


Is it correct? Is BOOT.oe = 1 means boot is tri-state ?

Any help will be very appreciated!

/If/ I remember ABEL... (and I might not, as it's some years since I
last used it)

aset is asynchronous set, aclr is asynchronous clear, oe is output
enable. All are assumed active high.

So I suspect your code should be more like:

process (RESET, IOWR)

begin
if (RESET = '1') then
BOOT <= '1';
elsif (falling_edge (IOWR)) then
BOOT <= (IOD0 and BOOT_BASE) or (BOOT and (not BOOT_BASE));
end if;
end process;

This is a case where I don't see the virtue in assigning to a
temporary variable.

It looks like a D type FF with enable, async preset and async clear,
with BOOT_BASE as the enable term. It also looks like the enable
has been generated from a product term rather than the device
supporting enable directly. In turn, this suggests another
possible simplification of the process:

begin
if (RESET = '1') then
BOOT <= '1';
elsif falling_edge (IOWR) then
if BOOT_BASE = '1' then
BOOT <= IOD0;
end if;
end if;
end process;

The fact that the oe term is 1 says it's /not/ 3-stated. (Since the
oe term is constant, it would be useless otherwise.)

As always, I reserve the right to be wrong!

Dave

 

[Steven P]

Hi, Dave,

Thank you very much for the help.

I forgot to quote the line of "RESET" declaration, it is

!RESET pin;

so it is low active, therefore I write "if (RESET = '0') then ... ".

Assume RESET is active High, you wrote

if (RESET = '1') then
BOOT <= '1';

Now I have another question about .aclr:
Do .aclr = 0 means the value of reg will be set to '1', or does it
depents on the declaration of RESET? Does it have something to do with
..aset = RESET?

I also have following addtional code to translate:

IN8 pin;

NOTAUS pin istype 'retain';
NOTAUS = !IN8 # (NOTAUS.pin & !RES_FF);

How can I infer FF( note register, no clock) for NOTAUS in VHDL? What
is "retain" in VHDL? I got looping warning when I wrote

port(
NOTAUS: std_logic;
)
....

signal NOTAUS_tmp: std_logic;
NOTAUS_tmp <= (not IN8) or (NOTAUS_tmp and (not RES_FF));
NOTAUS <= NOTAUS_tmp;


Thanks

Steven

 

[davehigton]

Hi, Dave,

Thank you very much for the help.

I forgot to quote the line of "RESET" declaration, it is

!RESET pin;

so it is low active, therefore I write "if (RESET = '0') then ... ".

Assume RESET is active High, you wrote


Now I have another question about .aclr:
Do .aclr = 0 means the value of reg will be set to '1', or does it
depents on the declaration of RESET? Does it have something to do with
.aset = RESET?

In the world of logic design, we preset to 1 and we clear to 0. We
don't preset to 0; we don't clear to 1. .aset means asynchronous
preset (i.e. to 1); .aclr means asynchronous clear (i.e. to 0). I've
just checked this with an old ABEL reference manual that I still have.

So the value that the register BOOT is set to is nothing to do with the
polarity of RESET. The polarity of RESET determines only what level
has to be applied to RESET in order to activate RESET.

In your original ABEL, RESET (or !RESET) was connected to BOOT.aset,
therefore a logic low applied to !RESET will asynchronously preset BOOT
to 1.

I also have following addtional code to translate:

IN8 pin;

NOTAUS pin istype 'retain';
NOTAUS = !IN8 # (NOTAUS.pin & !RES_FF);

How can I infer FF( note register, no clock) for NOTAUS in VHDL? What
is "retain" in VHDL?

The ABEL manual entry for 'retain' says:

"Do not minimize this output. Preserve redundant product terms for the
signal. This attribute must be used in conjunction with the "reduce
none" option in PLAOPT."

What you have in the above code is a latch. It is preset by IN8 and
cleared by RES_FF. Preset overrides clear. Again, note the
polarities of both of those signals.

Try something like:

process (NOTAUS, IN8, RES_FF)
begin
if IN8 = '1' then
NOTAUS <= '1';
elsif RES_FF = '1' then
NOTAUS <= '0';
end if;
end process;

Again, an intermediate signal doesn't help, IMHO.

One other thing: it would help if you used a proper interleaved posting
style.

Dave

 

[Steven P]

Thanks for the explanation of .aSet and .aClr pins.

I was a little confused by the automatic Invert feature in ABEL. So
when I saw
BOOT.aClr = 0, I thought it would be reset to 0, but actually it means
the reset pin of the FF is not used.

In the world of logic design, we preset to 1 and we clear to 0. We
don't preset to 0; we don't clear to 1. .aset means asynchronous
preset (i.e. to 1); .aclr means asynchronous clear (i.e. to 0). I've
just checked this with an old ABEL reference manual that I still have.

So the value that the register BOOT is set to is nothing to do with the
polarity of RESET. The polarity of RESET determines only what level
has to be applied to RESET in order to activate RESET.

In your original ABEL, RESET (or !RESET) was connected to BOOT.aset,
therefore a logic low applied to !RESET will asynchronously preset BOOT
to 1.


The ABEL manual entry for 'retain' says:

"Do not minimize this output. Preserve redundant product terms for the
signal. This attribute must be used in conjunction with the "reduce
none" option in PLAOPT."

What you have in the above code is a latch. It is preset by IN8 and
cleared by RES_FF. Preset overrides clear. Again, note the
polarities of both of those signals.

Try something like:

process (NOTAUS, IN8, RES_FF)
begin
if IN8 = '1' then
NOTAUS <= '1';
elsif RES_FF = '1' then
NOTAUS <= '0';
end if;
end process;

Again, an intermediate signal doesn't help, IMHO.

Thanks for the code for inferring the Latch.

The reason I use intermediate signal is that they will be used at other
places. ABEL seems not very strict on reading the output pins.