need help... VHDL Variable problem...

[elements_me]

my variable （ADDER)　value don't know y change to some others value @@... can everybody help me... my codes is below...

ENTITY neo IS
PORT ( I_10 , I_20 , I_50 : IN STD_LOGIC;
X : IN STD_LOGIC;
clk : IN STD_LOGIC;
END neo;

ARCHITECTURE beha OF neo IS

TYPE states IS ( SR , S0 );
SIGNAL state : states;
SIGNAL CD : STD_LOGIC_VECTOR ( 5 DOWNTO 0 );
SIGNAL E : STD_LOGIC;
SIGNAL EX : STD_LOGIC;
SIGNAL RD1 , RD2 : STD_LOGIC :='0' ;
SIGNAL S_ADDER : INTEGER range 0 to 140 := 0;
SIGNAL ID : STD_LOGIC_VECTOR ( 2 DOWNTO 0 );

BEGIN

ID <= I_50 & I_20 & I_10;
CD <= R & E & X & S & EX;

PROCESS ( clk , state , X , I_10 , I_20 , I_50 )
VARIABLE A_A , A_B , A_C , A_10 , A_20 , A_50 : INTEGER;
VARIABLE ADDER : INTEGER := 0;
BEGIN
IF rising_edge ( clk ) THEN
CASE state IS
WHEN SR =>
IF ( RD1 = '1' ) THEN
ADDER := 0;
T_ADDER := 0;
A_10 := 100;
A_20 := 100;
A_50 := 100;
E <= '0';
EX <= '0';
RD2 <= '1';
END IF;

WHEN S0 =>
IF ( ADDER < 100 ) THEN
CASE ID IS
WHEN "001" =>
ADDER := ADDER + 10;
WHEN "010" =>
ADDER := ADDER + 20;
WHEN "100" =>
ADDER := ADDER + 50;
WHEN OTHERS =>
NULL;
END CASE;
END IF;

state SR will go to state S0 after those value reset ( no show in the code ) ... the problem is the value of ADDER,,, let's said I_50 = '1'... the ID = "100"... and ADDER should be 50... but the face is when i see the timing diagram... the adder value is not 50... it is something else... like 32 like that... how come ??? help... really take me long time to check it le...:-(