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Hello, I have a major LAB homework assignment that we are alotted three weeks to do. Given I have spent 40 hours already on LAB Homework assignment two and I have read assignment 3 thoroughly. I can tell you that I need all the help I can get; Whatever "useful" info I can get will allow me three afternoon's to do the assignment. I work 55 hours a week provided with a laptop (to take home for 55 hour week - e-mail's from suppliers) and go to school entire week taking 4 credits each class which allows me only about 12 total hours to do problems. I have had to do homework beyond midnight to 3:00 a.m. to make up time which means 4 hours a night for sleep.
SO - BELOW is the assignment. I do not start it until we have covered material this week but you will see the outline says you are on your own on this...
Note: It is a lengthy problem. I assume most of you will come up with statements like "not here to do your HW". That is clear! Actually, I wouldn't do yours either - even "if" I had the time! That said, I would not ask if I thought "all" the folks on this forum were like me.
Here it is: "State Machine Controllers:"
Design an arithmetic circuit (parallel multiply/adder).
No, the instructor has not told us or shown us these components or how to do these items yet; This is only our third lab!
He has said quote:
"You are on your own to implement this lab problem aside from the following suggestion: "this is 'bootcamp' for next term - deal with it!":
Problem:
1. Design has to be able to add or multiply two 8-bit values. When multiplying, a product of up to 16 bits will be generated. When adding, a sum of up to 9 bits will be generated.
2. A register, called an "accumulator", is to hold the results of the calculation as well as one of the operands. The accumulator is to be "16 bits in size".
3. The value of the accumulator is constantly displayed on the FPGA (nexys II board) 7-segment LED's as a 4-digit hexadecimal (radix 16) value.
4. The row of 8 slide switches on the FPGA (Nexys II board) provides the second operand for the addition/multiplication.
5. Three pushbuttons of the FPGA board are used to initiate operations.
1. The RESET pushbutton will reset the accumulator to a value of 0.
2. The ADD pushbutton will add the value set on the switches to the value in the accumulator, placing the sum in the accumulator.
3. The MULTIPLY pushbutton will multiply the value set on the switches by the value in the accumulator, placing the product in the accumulator.
6. All three pushbuttons are to have synchronizer and low pass filter circuits to eliminate clock bounce and align signal edges with the clock. However they may not use the one-shot circuit used in lab units 1, 2, and 3.
7. The ADD and MULTIPLY pushbuttons are to cause no action until they have been released. In other words, a press and release cycle is needed to cause the action to take place. This prevents more than one add or multiply per press.
8. If the value in the accumulator is greater than 255 (00FF in hexadecimal) the ADD and MULTIPLY buttons are not to perform any arithmetic, but instead an LED, "Overflow", is to be lit when the button is released. The LED is to stay lit until the accumulator is reset.
9. Execution when more than one button is pressed simultaneously is undefined.
10.A Mealy State Machine is to be used to control the arithmetic circuits and light the overflow LED.
There are values, A, b, C, d, E, and F generated with the values
"10001000", "10000011", "11000110", "10100001", "10000110", and "10001110", respectively.
To simulate your design, change the length of your counter in a digitally created "low pass filter" to 2 bits and use "button presses" that are 4 clock periods long. Add the accumulator register to the timing display so you can see what its contents are (it would be too difficult to justlook at the 7 segment display levels). The simulation should press the reset button (the
accumulator should contain zero), set the switches to "10001000", press the add button (the accumulator should contain 0088 hexadecimal), set the switches to "01110111" and press the add button again (accumulator contains 00FF), set the switches to "11111111" and press the multiply button (accumulator contains FE01). Add additional tests to the simulation to show that requirement 8 (the overflow LED) is being met.
SO - BELOW is the assignment. I do not start it until we have covered material this week but you will see the outline says you are on your own on this...
Note: It is a lengthy problem. I assume most of you will come up with statements like "not here to do your HW". That is clear! Actually, I wouldn't do yours either - even "if" I had the time! That said, I would not ask if I thought "all" the folks on this forum were like me.
Here it is: "State Machine Controllers:"
Design an arithmetic circuit (parallel multiply/adder).
No, the instructor has not told us or shown us these components or how to do these items yet; This is only our third lab!
He has said quote:
"You are on your own to implement this lab problem aside from the following suggestion: "this is 'bootcamp' for next term - deal with it!":
Problem:
1. Design has to be able to add or multiply two 8-bit values. When multiplying, a product of up to 16 bits will be generated. When adding, a sum of up to 9 bits will be generated.
2. A register, called an "accumulator", is to hold the results of the calculation as well as one of the operands. The accumulator is to be "16 bits in size".
3. The value of the accumulator is constantly displayed on the FPGA (nexys II board) 7-segment LED's as a 4-digit hexadecimal (radix 16) value.
4. The row of 8 slide switches on the FPGA (Nexys II board) provides the second operand for the addition/multiplication.
5. Three pushbuttons of the FPGA board are used to initiate operations.
1. The RESET pushbutton will reset the accumulator to a value of 0.
2. The ADD pushbutton will add the value set on the switches to the value in the accumulator, placing the sum in the accumulator.
3. The MULTIPLY pushbutton will multiply the value set on the switches by the value in the accumulator, placing the product in the accumulator.
6. All three pushbuttons are to have synchronizer and low pass filter circuits to eliminate clock bounce and align signal edges with the clock. However they may not use the one-shot circuit used in lab units 1, 2, and 3.
7. The ADD and MULTIPLY pushbuttons are to cause no action until they have been released. In other words, a press and release cycle is needed to cause the action to take place. This prevents more than one add or multiply per press.
8. If the value in the accumulator is greater than 255 (00FF in hexadecimal) the ADD and MULTIPLY buttons are not to perform any arithmetic, but instead an LED, "Overflow", is to be lit when the button is released. The LED is to stay lit until the accumulator is reset.
9. Execution when more than one button is pressed simultaneously is undefined.
10.A Mealy State Machine is to be used to control the arithmetic circuits and light the overflow LED.
There are values, A, b, C, d, E, and F generated with the values
"10001000", "10000011", "11000110", "10100001", "10000110", and "10001110", respectively.
To simulate your design, change the length of your counter in a digitally created "low pass filter" to 2 bits and use "button presses" that are 4 clock periods long. Add the accumulator register to the timing display so you can see what its contents are (it would be too difficult to justlook at the 7 segment display levels). The simulation should press the reset button (the
accumulator should contain zero), set the switches to "10001000", press the add button (the accumulator should contain 0088 hexadecimal), set the switches to "01110111" and press the add button again (accumulator contains 00FF), set the switches to "11111111" and press the multiply button (accumulator contains FE01). Add additional tests to the simulation to show that requirement 8 (the overflow LED) is being met.
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