Need some help!

Discussion in 'VHDL' started by bhiggins@umr.edu, Apr 12, 2005.

  1. Guest

    I am able to synthesize this code, but the LED stays on constantly. Can
    anyone see something wrong with my code that is listed below? I have a
    very simple schematic with CLK (1.8432MHz) coming in and LED going out.


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    -- Uncomment the following lines to use the declarations that are
    -- provided for instantiating Xilinx primitive components.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity newtrycode is
    Port ( CLK : in std_logic;
    LED : out std_logic);
    end newtrycode;

    architecture Behavioral of newtrycode is

    begin

    flash:process(CLK)

    variable temp2: integer:=0;
    variable temp1: integer:=0;

    begin

    if CLK = '1' and CLK'event then
    temp2 := temp2 + 1;
    end if;

    if temp2 = 921600 and temp1 = 1 then
    LED <= '0';
    temp1 := 0;
    temp2 := 0;
    end if;

    if temp2 = 921600 and temp1 = 0 then
    LED <= '1';
    temp1 := 1;
    temp2 := 0;
    end if;


    end process flash;

    end Behavioral;
     
    , Apr 12, 2005
    #1
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  2. Praveen Guest

    Well that is because you only have clk in the senstivity list and
    moreover you are doing in a long way. Why dont u do something like

    if(rising_edge(clk)) then
    if(temp2 = 921600) then
    Light led;
    temp2 := 0;
    else
    temp2 := temp2 + 1;
    Turnoffled;
    end if;
    end if;
     
    Praveen, Apr 12, 2005
    #2
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