Need suggestion abt FFs without RST for pipelined datapath.

Discussion in 'VHDL' started by john.deepu@gmail.com, Mar 2, 2005.

  1. Guest

    Hi all,
    I am currently implementing a module which has large number of
    registers(the datapath is heavily pipelined and lotsa registers). To
    reduce the area of the design , I have replaced many of the internal
    registers ,with FFs without a RESET pin.
    So now all the internal register dont get cleared (reset) while
    applying an external reset. they just keep on shifting unknown value,
    until the actual data fills in the pipeline. this is perfectly
    acceptable for me except for the initial X's I see in waveform, till
    the actual data reaches to the point.

    I save around 10-15% area by this way. (in a total size of ~90K).
    My module is part of a ~1.5Mgates asic.

    I want to ask you people , whether this method of reducing area will
    cause any problems(in the design flow) considering the total system.

    please giveme ur valuable suggestions.

    thanks a lot
    Deepu John
     
    , Mar 2, 2005
    #1
    1. Advertising

  2. wrote:
    > Hi all,
    > I am currently implementing a module which has large number of
    > registers(the datapath is heavily pipelined and lotsa registers). To
    > reduce the area of the design , I have replaced many of the internal
    > registers ,with FFs without a RESET pin.
    > So now all the internal register dont get cleared (reset) while
    > applying an external reset. they just keep on shifting unknown value,
    > until the actual data fills in the pipeline. this is perfectly
    > acceptable for me except for the initial X's I see in waveform, till
    > the actual data reaches to the point.
    >
    > I save around 10-15% area by this way. (in a total size of ~90K).
    > My module is part of a ~1.5Mgates asic.
    >
    > I want to ask you people , whether this method of reducing area will
    > cause any problems(in the design flow) considering the total system.
    >
    > please giveme ur valuable suggestions.
    >
    > thanks a lot
    > Deepu John
    >


    One problem can occur with back annotated gate sims. It is possible to
    create logic that works but cannot be simulated unless you have a way
    to initialize registers to a known value. (Anything but X).

    But as you noticed it can be costly to put a reset on every flop in the
    design. Not only is there an area cost but you have to route that reset
    around the entire chip and meet setup/hold timing on every flop.

    I like the idea of multicycle resets where you are required to hold a reset
    for X number of cycles. Then as long as you can reset everything by cycle
    X then everything will work.

    John Eaton
     
    J o h n _ E a t o n (at) hp . com (no spaces), Mar 2, 2005
    #2
    1. Advertising

  3. KCL Guest

    For simulation probleme you could put a value to your signal when you
    declare it
    like:

    signal temp : std_logic :='0';
    like that it will have an initial value different from X at start but will
    not be synthetized

    Alexis

    "J o h n _ E a t o n (at) hp . com (no spaces)" <"J o h n _ E a t o n (at)
    hp . com (no spaces)"> a écrit dans le message de news:
    42263428$...
    > wrote:
    >> Hi all,
    >> I am currently implementing a module which has large number of
    >> registers(the datapath is heavily pipelined and lotsa registers). To
    >> reduce the area of the design , I have replaced many of the internal
    >> registers ,with FFs without a RESET pin.
    >> So now all the internal register dont get cleared (reset) while
    >> applying an external reset. they just keep on shifting unknown value,
    >> until the actual data fills in the pipeline. this is perfectly
    >> acceptable for me except for the initial X's I see in waveform, till
    >> the actual data reaches to the point.
    >>
    >> I save around 10-15% area by this way. (in a total size of ~90K).
    >> My module is part of a ~1.5Mgates asic.
    >>
    >> I want to ask you people , whether this method of reducing area will
    >> cause any problems(in the design flow) considering the total system.
    >>
    >> please giveme ur valuable suggestions.
    >>
    >> thanks a lot
    >> Deepu John
    >>

    >
    > One problem can occur with back annotated gate sims. It is possible to
    > create logic that works but cannot be simulated unless you have a way
    > to initialize registers to a known value. (Anything but X).
    >
    > But as you noticed it can be costly to put a reset on every flop in the
    > design. Not only is there an area cost but you have to route that reset
    > around the entire chip and meet setup/hold timing on every flop.
    >
    > I like the idea of multicycle resets where you are required to hold a
    > reset
    > for X number of cycles. Then as long as you can reset everything by cycle
    > X then everything will work.
    >
    > John Eaton
    >
    >
    >
    >
    >
    >
    >
     
    KCL, Mar 2, 2005
    #3
  4. nonoe Guest

    "KCL" <> wrote in message
    news:422642ed$0$25040$...
    > For simulation probleme you could put a value to your signal when you
    > declare it
    > like:
    >
    > signal temp : std_logic :='0';
    > like that it will have an initial value different from X at start but will
    > not be synthetized


    Perhaps that works easily with VHDL, but many Verilog synthesis tools
    may reject the equivalent:

    reg q;

    initial q = 1'b0; // for simulation-only!

    .....
    (or for a more modern Verilog-2001 tool)

    reg q = 1'b0;
     
    nonoe, Mar 3, 2005
    #4
  5. Hi,

    wrote:
    > reduce the area of the design , I have replaced many of the internal
    > registers ,with FFs without a RESET pin.

    [..]
    > I want to ask you people , whether this method of reducing area will
    > cause any problems(in the design flow) considering the total system.


    If you insert these FF in a scan chain, you could not reset them.
    I was told that this will be not acceptable for the ASIC vendor. Maybe you
    should check the needs of your vendor.

    bye Thomas

    --
    Emailantworten bitte an thomas[at]obige_domain.
    Usenet_10 ist für Viren und Spam reserviert
     
    Thomas Stanka, Mar 3, 2005
    #5
  6. Ray Andraka Guest

    wrote:

    >Hi all,
    > I am currently implementing a module which has large number of
    >registers(the datapath is heavily pipelined and lotsa registers). To
    >reduce the area of the design , I have replaced many of the internal
    >registers ,with FFs without a RESET pin.
    >So now all the internal register dont get cleared (reset) while
    >applying an external reset. they just keep on shifting unknown value,
    >until the actual data fills in the pipeline. this is perfectly
    >acceptable for me except for the initial X's I see in waveform, till
    >the actual data reaches to the point.
    >
    >I save around 10-15% area by this way. (in a total size of ~90K).
    >My module is part of a ~1.5Mgates asic.
    >
    >I want to ask you people , whether this method of reducing area will
    >cause any problems(in the design flow) considering the total system.
    >
    >please giveme ur valuable suggestions.
    >
    >thanks a lot
    >Deepu John
    >
    >
    >

    generally, it won't cause a problem except for with ASIC folks who don't
    accept anything less than 100% reset. You can make the reset totally
    invisible by a) making sure you break all internal loops by forcing a
    reset on one element in the loop and holding that reset for enough
    clocks to make the known data propagate all the way around the loop, and
    b) putting reset on all the output registers that is applied immediately
    and then held until good data propagates to the output register. The
    output register reset can easily be accomplished by using a sync RS-FF
    that is set by the reset input signal and then cleared by either a
    delayed version of the input reset signal or using a counter that is
    preset by the input reset signal and whose terminal count clears that
    FF. Same is true for the loop resets.

    --
    --Ray Andraka, P.E.
    President, the Andraka Consulting Group, Inc.
    401/884-7930 Fax 401/884-7950
    email
    http://www.andraka.com

    "They that give up essential liberty to obtain a little
    temporary safety deserve neither liberty nor safety."
    -Benjamin Franklin, 1759
     
    Ray Andraka, Mar 3, 2005
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. walala
    Replies:
    3
    Views:
    5,723
    walala
    Aug 30, 2003
  2. Fred Bartoli

    Pipelined binary encoder

    Fred Bartoli, Nov 7, 2004, in forum: VHDL
    Replies:
    1
    Views:
    748
    Jonathan Bromley
    Nov 10, 2004
  3. Shenli

    Datapath design problem?

    Shenli, Jan 26, 2007, in forum: VHDL
    Replies:
    2
    Views:
    581
    Ray Andraka
    Jan 28, 2007
  4. jacob navia

    ffs function

    jacob navia, Jan 6, 2008, in forum: C Programming
    Replies:
    10
    Views:
    1,534
    user923005
    Jan 7, 2008
  5. alexandis

    Find treenode by DataPath, not ValuePath

    alexandis, Feb 1, 2008, in forum: ASP .Net
    Replies:
    2
    Views:
    512
    alexandis
    Feb 1, 2008
Loading...

Share This Page