K
kasthuri.m92
i need vhd for genetic algorithm in evolvable hardware design.
i need vhd for genetic algorithm in evolvable hardware design.
i need vhd for genetic algorithm in evolvable hardware design.
if sex_prob = '1' thenlibrary ieee;
use ieee.std_logic_1164.all;
entity evolvable_hardware is
port (
reset : in std_logic;
clk : in std_logic;
d : in std_logic; dsex : in std_logic;
q : out std_logic;
);
end entity evolvable_hardware;
architecture evolve of evolvable_hardware is
begin
reg_proc : process(clk)
begin
if reset = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= (d XOR mutate_prob) ; end if;
end if;
end process;
end architecture evolve;
I bet something like this could eventually evolve into an FFT?
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