needed basics of FIFO design and in writing test benches

Discussion in 'VHDL' started by chaitu, Feb 19, 2007.

  1. chaitu

    chaitu Guest

    hai every body,
    i want to design a FIFO interface in a SOC either synchronous /
    asynchronous where i can foind the basics of FIFO and i also want to
    have basic material to write good testbenches.. can any one help me.
    thanks in advance
     
    chaitu, Feb 19, 2007
    #1
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  2. chaitu wrote:

    > i want to design a FIFO interface in a SOC either synchronous /
    > asynchronous where i can foind the basics of FIFO and i also want to
    > have basic material to write good testbenches.. can any one help me.
    > thanks in advance


    see the testbench and sync_fifo examples here:
    http://home.comcast.net/~mike_treseler/

    -- Mike Treseler
     
    Mike Treseler, Feb 19, 2007
    #2
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  3. chaitu

    JK Guest

    On Feb 19, 2:21 pm, "chaitu" <> wrote:
    > hai every body,
    > i want to design a FIFO interface in a SOC either synchronous /
    > asynchronous where i can foind the basics of FIFO and i also want to
    > have basic material to write good testbenches.. can any one help me.
    > thanks in advance


    try opencores.org
     
    JK, Feb 21, 2007
    #3
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