needs help on CLOCK

[vx100miles]

Hello everyone,
Good Day.

I want to download the following VHDL code to FPGA Xilinx Virtex-4.

process(clk)
begin
if (clk'event and clk = '1') then
if (cycle = '0') then
x <= a;
cycle <= '1';
else
x <= b;
cycle <= '0';
end if;
end if;
end process;

I have downloaded this to the FPGA. I have given input by DIP switch (An active low signal is generated when a given switch is ON) and output is in LED (turned “ON” by driving the LEDx signal to logic “0”). the result is as follows:

1. when a=11 and b=11 (by DIP switch), ALL output LED is OFF
2. when a=01 and b=01 , x(1) is MORE BRIGHT, x(0) is OFF
3. when a=11 and b=01 , x(1) is LESS BRIGHT, x(0) is OFF

Can I explain the result like this, because of the RAPID clocking, x changes rapidly. When it has the same value as previous, it is BRIGHT. and when it has different values, it is less bright.

I am using CLK_100 (System Clock – This clock input is connected to a 100MHz LVTTL oscillator) as clk. How can I control the clock speed?

regards and thanks in advance

pantho

 

[Ardni]

Hi pantho,
Probably the easiest way to control the speed at which the LED´s change is to code in a delay into your process. You could experiment with something like the modification shown below.
You may also need some form of reset to reset the delay integer to 0 if you have one of the DIP switches available.
Also experiemnt with the value of delay, I put 18000, maybe this is too much or too little, mess around with it until you find a value that suits, or do the maths and figure out the correct time delay that you want.

process(clk)
variable delay : integer;
begin
if (clk'event and clk = '1') then
delay := delay := delay + 1;

if (delay = 18000) then --experiment with this value
delay:= 0;
if (cycle = '0') then
x <= a;
cycle <= '1';
else
x <= b;
cycle <= '0';
end if;
end if;
end if;
end process;


Hope this helps.

 

[vx100miles]

thank you

thank you Ardni. It works fine.