Negative setup and Negative hold

Discussion in 'VHDL' started by prem_eda, Oct 11, 2004.

  1. prem_eda

    prem_eda Guest

    What is the practical implication of negative setup and negative hold?
    How do simulators handle negative timing checks?
    prem_eda, Oct 11, 2004
    #1
    1. Advertising

  2. prem_eda wrote:

    > What is the practical implication of negative setup and negative hold?
    > How do simulators handle negative timing checks?


    Setup and hold together just define the time during which the input signal
    should not change in order to get a stable output. Having either a negative
    setup or a negative hold (both at the same time is very unlikely:) just
    places that stable period before (negative hold) or after (negative setup)
    the clock edge i.s.o. around it. I see no reason why a simulator would have
    any problems with this.

    Regards,

    Pieter Hulshoff
    Pieter Hulshoff, Oct 11, 2004
    #2
    1. Advertising

  3. prem_eda

    prem_eda Guest

    Whenever we perform Timing simulation, the SDF file contains Timing check
    tasks (For example $setuphold) constructs which has some negative
    values.Normally, the simulator has a negative timing constraint algorithm
    to handle the -ve values in the timing check tasks and in some cases I see
    that being rounded off to zero.
    So,any one you guys have faced this? Why is the simulator doin this?
    prem_eda, Oct 11, 2004
    #3
  4. prem_eda wrote:
    > Whenever we perform Timing simulation, the SDF file contains Timing check
    > tasks (For example $setuphold) constructs which has some negative
    > values.Normally, the simulator has a negative timing constraint algorithm
    > to handle the -ve values in the timing check tasks and in some cases I see
    > that being rounded off to zero.
    > So,any one you guys have faced this? Why is the simulator doin this?


    Hmm, a tad more information would be nice.
    1. Which simulator are you running?
    2. How much is th negative timing constraint?
    3. What is your simulation resolution?

    One reason I could think of is that the negative timing constraint is
    smaller than your simulation resolution, but perhaps other reasons may pop
    up if you can give a few more specifics. You say 'in some cases'; I presume
    that means that sometimes it's handled correctly?

    Regards,

    Pieter Hulshoff
    Pieter Hulshoff, Oct 11, 2004
    #4
  5. prem_eda

    prem_eda Guest

    I am using Modelsim SE version 5.8c on Windows 2000 platform.The simulator
    resolution is in ns and the SDF file has a a ps resolution.I do not have
    the SDF file with me But I can just quote an example which is something
    like this.
    $setuphold( posedge s1clk, negedge wr_en1, 180, -74,
    notifier,,,ds1clk,dd);
    prem_eda, Oct 11, 2004
    #5
  6. prem_eda wrote:
    > I am using Modelsim SE version 5.8c on Windows 2000 platform.The simulator
    > resolution is in ns and the SDF file has a a ps resolution.I do not have
    > the SDF file with me But I can just quote an example which is something
    > like this.
    > $setuphold( posedge s1clk, negedge wr_en1, 180, -74,
    > notifier,,,ds1clk,dd);


    Are you sure your simulator uses a resolution of 1 ns? If it is, then any
    time setting will be chopped down to a number x 1 ns, e.g. 3.9 ns => 3 ns,
    1.1 ns => 1 ns, 150 ps => 0 ns. You might want to see what results you get
    if you set your simulation resolution to 10 ps or 1 ps.

    Regards,

    Pieter Hulshoff
    Pieter Hulshoff, Oct 11, 2004
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Replies:
    7
    Views:
    23,197
  2. ed

    Setup and Hold Times

    ed, Dec 8, 2004, in forum: VHDL
    Replies:
    1
    Views:
    947
    Mike Treseler
    Dec 9, 2004
  3. maazbecin

    why "setup-time and hold-time"?

    maazbecin, Jul 24, 2006, in forum: VHDL
    Replies:
    0
    Views:
    3,141
    maazbecin
    Jul 24, 2006
  4. Replies:
    0
    Views:
    476
  5. luvdhams23

    D flip flop setup and hold timings.

    luvdhams23, Jun 3, 2010, in forum: VHDL
    Replies:
    0
    Views:
    954
    luvdhams23
    Jun 3, 2010
Loading...

Share This Page