Nested "generate" statements

Discussion in 'VHDL' started by wjsimons, Nov 6, 2006.

  1. wjsimons

    wjsimons

    Joined:
    Nov 6, 2006
    Messages:
    1
    Hi,

    I'm trying to write something like:

    gen1: FOR J IN 5 DOWNTO 0 GENERATE
    gen2: FOR I IN 7 DOWNTO 0 GENERATE
    gen3: IF ( I = J + 2 ) GENERATE
    ...

    If I use the above, not a single component is instantiated. If I replace the last line by
    gen3: IF ( I = 7 ) GENERATE

    then it does work. In fact, as soon as I add a line comparing both of the two variables of the outer generate statements, things go wrong. I did find examples on the net where it is done this way.

    Does anyone know why everything gets synthetised away?

    Thanks,
    W
    wjsimons, Nov 6, 2006
    #1
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