# nesting counters

Discussion in 'VHDL' started by john, May 8, 2006.

1. ### johnGuest

Hi,

I need some guide lines to cascade three counters. I have two 5 bit
counters ( A and B) and one 14 bit counter ( C). Counter 'A' counts
upto 32 and increment Counter B by one and when counter B will reach to
32 it will increment counter C by one. The maximum count for counter C
is 256.
Should I increment the counter B at the falling edge of the MSB of the
counter A?
Should I increment the counter C on the falling edge of the counter B?

Please advice!
John

john, May 8, 2006

2. ### Andrew FPGAGuest

Make sure you use the same clock for all the counters. Keep it
synchronous.
e.g. increment counter B when counter A = 31.

variable countB : natural range 0 to 31;
....

--Counter B
if rising_edge(clock) then
if countA = 31 then
countB := (CountB + 1) mod 32;
end if;
end if;

john wrote:
> Hi,
>
> I need some guide lines to cascade three counters. I have two 5 bit
> counters ( A and B) and one 14 bit counter ( C). Counter 'A' counts
> upto 32 and increment Counter B by one and when counter B will reach to
> 32 it will increment counter C by one. The maximum count for counter C
> is 256.
> Should I increment the counter B at the falling edge of the MSB of the
> counter A?
> Should I increment the counter C on the falling edge of the counter B?
>
> Please advice!
> John

Andrew FPGA, May 8, 2006

3. ### johnGuest

Hi,

Thanks for the reply! I was wondering that why do we need mod 32. would
u please advice me. Thanks
Regards
John
Andrew FPGA wrote:
> Make sure you use the same clock for all the counters. Keep it
> synchronous.
> e.g. increment counter B when counter A = 31.
>
> variable countB : natural range 0 to 31;
> ...
>
> --Counter B
> if rising_edge(clock) then
> if countA = 31 then
> countB := (CountB + 1) mod 32;
> end if;
> end if;
>
>
>
>
> john wrote:
> > Hi,
> >
> > I need some guide lines to cascade three counters. I have two 5 bit
> > counters ( A and B) and one 14 bit counter ( C). Counter 'A' counts
> > upto 32 and increment Counter B by one and when counter B will reach to
> > 32 it will increment counter C by one. The maximum count for counter C
> > is 256.
> > Should I increment the counter B at the falling edge of the MSB of the
> > counter A?
> > Should I increment the counter C on the falling edge of the counter B?
> >
> > Please advice!
> > John

john, May 9, 2006
4. ### Andrew FPGAGuest

Hi John,
Mod forces the rollover from 31 to 0. Actually XST(xilinx) won't
synthesise the mod operator if your count variable is not a power of 2
range. Instead you could test for the count = 31 and then assign 0 to
the count to achieve rollover.
Regards
Andrew

john wrote:
> Hi,
>
> Thanks for the reply! I was wondering that why do we need mod 32. would
> u please advice me. Thanks
> Regards
> John
> Andrew FPGA wrote:
> > Make sure you use the same clock for all the counters. Keep it
> > synchronous.
> > e.g. increment counter B when counter A = 31.
> >
> > variable countB : natural range 0 to 31;
> > ...
> >
> > --Counter B
> > if rising_edge(clock) then
> > if countA = 31 then
> > countB := (CountB + 1) mod 32;
> > end if;
> > end if;
> >
> >
> >
> >
> > john wrote:
> > > Hi,
> > >
> > > I need some guide lines to cascade three counters. I have two 5 bit
> > > counters ( A and B) and one 14 bit counter ( C). Counter 'A' counts
> > > upto 32 and increment Counter B by one and when counter B will reach to
> > > 32 it will increment counter C by one. The maximum count for counter C
> > > is 256.
> > > Should I increment the counter B at the falling edge of the MSB of the
> > > counter A?
> > > Should I increment the counter C on the falling edge of the counter B?
> > >
> > > Please advice!
> > > John

Andrew FPGA, May 9, 2006
5. ### johnGuest

Hi,

I nee CountB, Count C and CountA are in different processes. How can I
make them shared in different processes. first I do not know how to
make them global. Advice needed! and then will it create any problems
later.

Thanks
John

john, May 11, 2006
6. ### Mike TreselerGuest

john wrote:

> I nee CountB, Count C and CountA are in different processes.

Why? Simpler is better.

> How can I
> make them shared in different processes.

Processes communicate using signals.
Look it up.

-- Mike Treseler

Mike Treseler, May 11, 2006
7. ### johnGuest

Hi,

But the problem is that my design needs to increment the counters on
the falling edge of the MSB bit. That will take the main clock away
from the counters and they will not be synchronous anymore. how can I
do it without removing the clock and on the falling edge of the MSB
bit.

John

john, May 18, 2006
8. ### Mike TreselerGuest

john wrote:

> But the problem is that my design needs to increment the counters on
> the falling edge of the MSB bit. That will take the main clock away
> from the counters and they will not be synchronous anymore. how can I
> do it without removing the clock and on the falling edge of the MSB
> bit.

Generate a synchronous strobe
and use that as an enable.

-- Mike Treseler

Mike Treseler, May 18, 2006
9. ### johnGuest

Can u advice me example code?

John

john, May 18, 2006
10. ### Mike TreselerGuest

Mike Treseler, May 19, 2006
11. ### johnGuest

Hi,

The example u send me is little bit high level for me . Would you plz.
advice me that how can I add strobe signal to the counter. Right now I
have following counters. I have two 6 bit counters and one 14 bit
counter. I am using the 5th bit of the two counters as trigger to the
other counter. But I need something that can trigger the other counter
instantly. Because of this problem my whole project is not working
properly.

-- Frame Counter --
Process (Reset_out, DPR_CLK)
Begin
If (Reset_out ='1' )Then
Frame_cntr<=(others =>'0');

elsif rising_edge(DPR_CLK) then
If ( indicator_frame = '1') Then
Frame_cntr <= Frame_cntr + 1 ;
End If;
End If;
End Process;

Process (Reset_out, DPR_CLK)
Begin
If (Reset_out ='1') Then
countc_mux_datain <= (others =>'0');
elsif rising_edge(DPR_CLK) then
If (indicator_sample = '1') Then
countc_mux_datain <= countc_mux_datain + 1 ;
End If;
End If;
End Process;
indicator_frame <= countc_mux_datain (5) ;
-- Channel Counter routine Begins--
Process (Reset_out, DPR_CLK)
Begin

If( Reset_out ='1') Then
countb_mux_datain <= (others =>'0');

elsif rising_edge(DPR_CLK) then
if (incr_B='1') then
countb_mux_datain <= countb_mux_datain + 1;
End If;
End If;
End Process;

indicator_sample <= countb_mux_datain (5) ;

End DPR_ARCH;

Regards
John

john, May 19, 2006
12. ### Uncle NoahGuest

Hi there

some 2-3 years ago i had implemented a parameterizable "hardware
looping unit" featuring (fully) nested counters for looping over such
loop structures. You can specify the number of loops and generate part
of the VHDL description from C generators.

You can reach it (OpenCores CVS) at:
http://www.opencores.org/projects.cgi/web/hwlu/overview

This is an implementation in VHDL of something similar to the
"Mediabreeze looping unit" by D. Talla.

kind regards
Nikolaos Kavvadias

Uncle Noah, May 19, 2006
13. ### johnGuest

Hi,

Thanks for ur reply! But I am unable to understand how to get the
example. Please advice me in m ore detail.

John

john, May 21, 2006
14. ### johnGuest

Hi Mike,

I have following questions

1. Why strobe?
2. Would you advice me that how can I generate the strobe signal to
enable the other counters?

Regards,
John

john, May 22, 2006
15. ### Mike TreselerGuest

john wrote:

> 1. Why strobe?

This makes good use of the clock enable flops
and keeps things synched to one clock.

> 2. Would you advice me that how can I generate the strobe signal to
> enable the other counters?

With an and gate and an inverter.
See the pdf link again.

-- Mike Treseler

Mike Treseler, May 22, 2006
16. ### johnGuest

Hi Mike,

So, i need to use the MSB bit of the first counter to "AND" with the
same MSB bit via an inverter to increment the second counter.

So, it will be count_B _indicator < = countA(4) AND NOT countA(4)

Am I right?

John

john, May 22, 2006
17. ### Mike TreselerGuest

john wrote:

> So, i need to use the MSB bit of the first counter to "AND" with the
> same MSB bit via an inverter to increment the second counter.
> So, it will be count_B _indicator < = countA(4) AND NOT countA(4)

Try it and see.

-- Mike Treseler

Mike Treseler, May 22, 2006
18. ### johnGuest

I tried but it did not work. its not incrementing the other counter. I
suspect that I am not understanding ur drawing correctly. Do u have two
counters in ur design?
John

john, May 22, 2006
19. ### johnGuest

Hi mike,

you know what you are a good guy. you sincerely wants to help people
who are doing VHDL. you might have scarificed alot to learn VHDL or
digital systems etc. But sometimes poeple like me who do not have
enough experience and skills in VHDL needs more than just help to solve
their problems. I know that u have enough experience to see the posting
on the goole groups that how much this person knows about the VHDL. So,
If you do not like the question or u think its too easy for u or for
whatever reason, please do not try to answer that question because when
other people see that u replied that question , they just do not help.
There are some people who do want to help me but they do not because
they see ur name. i hope, u will understand.

John

john, May 22, 2006
20. ### Mike TreselerGuest

Mike Treseler, May 23, 2006

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