netlist from VHDL code

Discussion in 'VHDL' started by Ruby, Jun 29, 2005.

  1. Ruby

    Ruby Guest

    Hi,

    I am trying to simulate a cache compressor with some 8k data lines. I
    mean 8k lines are the input from L1 cache to the compressor. The
    compressor send the compressed output to the L2 cache or main memory.
    In this simulation I don't even want to verify the functionality - as
    an function(algorithm choosen for this compressor) can be implemented
    in a circuit form. I would like to find out the critical path of the
    circuit.

    Now my problem is since the circuit is too big(too many data lines),
    I don't want to draw the schematic. So Can I write the VHDL code for
    the circuit and get a netlist from the code. If I can do that, then I
    can run the pathmill to find the critical path of the circuit and so as
    the max. delay.

    Pls let me know if you guys have any suggestions.

    Thanks
    Ruby, Jun 29, 2005
    #1
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  2. Ruby wrote:

    > Now my problem is since the circuit is too big(too many data lines),
    > I don't want to draw the schematic.


    I wouldn't either.

    > So Can I write the VHDL code for
    > the circuit


    Yes. And a testbench for it to
    eliminate logical errors.

    > and get a netlist from the code. If I can do that, then I
    > can run the pathmill to find the critical path of the circuit and so as
    > the max. delay.


    Yes, a static timing analysis is the easiest way
    to find the critical paths.

    -- Mike Treseler.
    Mike Treseler, Jun 29, 2005
    #2
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  3. Ruby

    Ruby Guest

    > > So Can I write the VHDL code for
    > > the circuit

    >

    Yes. And a testbench for it to
    eliminate logical errors.

    What is the testbench and how to write it, Could you please mention in
    more detail.
    >
    > > and get a netlist from the code. If I can do that, then I
    > > can run the pathmill to find the critical path of the circuit and so as
    > > the max. delay.

    >
    > Yes, a static timing analysis is the easiest way
    > to find the critical paths.


    I guess to get nelist, vhdl code should be structural. Could you pls
    tell me, do the code have to be synthesizable code. I am not sure how
    to get the netlist out of vhdl code. Could you give me some pointer in
    that direction.

    Thanks
    Ruby, Jun 29, 2005
    #3
  4. Ruby wrote:

    > What is the testbench and how to write it, Could you please mention in
    > more detail.


    You need a vhdl tutorial, a book and a simulator to get started.
    Google this group for details. Do some research of your own.

    > I guess to get nelist, vhdl code should be structural.


    No. You need synthesis software.
    You need to learn to write and test
    vhdl code for synthesis.
    Here is an example:
    http://home.comcast.net/~mike_treseler/uart.vhd

    And a testbench:
    http://home.comcast.net/~mike_treseler/test_uart.vhd

    Good luck.

    -- Mike Treseler
    Mike Treseler, Jun 29, 2005
    #4
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