New Book: A Pragmatic Approach to VMM Adoption // for TB designs

Discussion in 'VHDL' started by hdlcohen@gmail.com, Jul 20, 2006.

  1. Guest

    The book A Pragmatic Approach to VMM Adoption ... a SystemVerilog
    Framework for Testbenches ISBN 0-9705394-9-5 is now available. For more
    information on the book, see http://www.systemverilog.us/vmm_info.html

    The book is co-authored by Ben Cohen, a well-known consultant and
    author of several technical books addressing the effective use of
    Verilog and VHDL for logic design and verification; Srinivasan
    Venkataramanan, Verification Solutions Applications Manager at Synopsys
    Inc.; and Ajeetha Kumari, Contemporary Verification Consultants Pvt.
    Ltd., a leading edge functional verification solutions provider based
    in Bangalore, India.

    With SystemVerilog becoming an IEEE standard, there is a growing user
    momentum in adopting this powerful language as it unified design,
    assertions and testbench. Early adaptors have quickly realized that a
    language with LRM of 700+ pages (on top of Verilog 2001, which is some
    400+ pages) is overwhelming and if not adopted correctly, users can
    quickly get trapped in the sheer volume of constructs. This is where a
    methodology and a framework really helps - it shifts the focus from
    language constructs to the actual goal - of building verification
    environments and the verification process itself.

    VMM, as co-developed by ARM and Synopsys, has been the first publicly
    available text/blueprint for successful verification architecture. The
    recently published VMM book has attracted lots of interest in the user
    community with over 3500 copies sold so far. VMM represents a
    methodology that includes a set of minimum practices that must be used
    to create interoperable and reusable verification assets. A methodology
    cannot be a training vehicle - nor can a training vehicle claim to be
    a methodology. A methodology, and the training it, requires to learn it
    and apply it effectively are two different things. Our book addresses
    the training and application of the VMM methodology, but references the
    rules defined in Janick's VMM book. Regardless of which framework you
    use, this book will enlighten you on what a well thought out framework
    can do.
    Quote:
    "I am pleased to welcome this book to the cannon of VMM literature. I
    hope you will find it helpful in appreciating the power of the VMM
    methodology and ease your adoption of it."
    Janick Bergeron, Synopsys Scientist.
    Quote:
    "The Pragmatic Approach to VMM Adoption teaches by example how the
    constructs in SystemVerilog are used to implement the methodology
    presented in the VMM. Similar to learning from an experienced mechanic
    how to use the right tools to repair a car, this book provides a way to
    learn from experts the right way to use SystemVerilog for verification,
    and makes it is much easier to understand how to apply the VMM
    methodology on actual designs."
    Stuart Sutherland, SystemVerilog instructor, President of Sutherland
    HDL, Inc.
    Quote:
    "A Pragmatic Approach to Adopting VMM is exactly what the doctor
    ordered for demystifying the VMM methodology and focusing users on the
    keys to applying it efficiently."
    Scott Sandler, President and CEO of Novas Inc.
    Quote:
    "Helps the reader to quickly get on board in the application of VMM
    for verification because it demonstrates through complete simulatable
    examples various approaches in building reusable VMM compliant
    testbenches. The book uses simple illustrations to explain the concepts
    involved in building of SystemVerilog based verification environments
    for complex SOCs."
    Vikas Gautam, Director, Corporate Applications Engineering,
    Verification Group, Synopsys
    Quote:
    "A Pragmatic Approach to Adopting VMM can be seen as a long overdue
    training on best practices for writing SystemVerilog-based testbenches.
    Companies should adopt this approach, if only to save cost, as
    verification engineers have better things to do than redevelop and
    learn a new testbench environment every time they change projects."
    Alain Raynaud, Technical Director, EVE USA, inc.

    _________________
    Ben Cohen Trainer, Consultant, Publisher (831) 345-1759
    http://www.systemverilog.us/
    * A Pragmatic Approach to VMM Adoption 0-9705394-9-5
    * SystemVerilog Assertions Handbook, 0-9705394-7-9
    * Using PSL/SUGAR
    * Real Chip Dsgn
     
    , Jul 20, 2006
    #1
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  2. nishit

    Joined:
    Aug 9, 2006
    Messages:
    1
    VMM Adoption

    Hello,

    Pragmatic approach book is a good source for adopting the VMM enviornment. It presents quiet well how to adopt the layered approach for chip verification. The VMM framework truely is a very systematic and structured approach. But I guess it might take while before the companies actually completely transfer their verification environment to this one.

    Examples and Labs to do in the book are very good and I guess it lays the foundation for some real concrete work. Concepts like Atomic generators, Scenario Generators, Call backs etc have been explained well.

    I would sincerely recommend anyone who's trying to get familiar with VMM try this book.

    Thanks,

    Nishit Dalia
    ASIC Design/Verification Engineer, EDN;
    Nortel Networks, Santa Clara.
     
    nishit, Aug 9, 2006
    #2
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