new to VHDL, question about arrays

[Joe26]

HI :barresed:

i'm trying to do the following thing:

Signal arr: std_logic_vector(1 downto 0);
Signal BitPos: integer:=0;

process(CLK)
begin

arr(BitPos) <= Din; --Din is std_logic type
BitPos <= BitPos + 1;

end process;

I'm trying to run a TestBench in which Din is set to '0' initialy and to '1' after 10ns. Now I understand how the process works and that BitPos is actually set to 1 before Din is inserted to arr, which means Din is inserted to arr(1) insted of arr(0). All i want to do is instering the first Din into arr(0) and the second Din into arr(1).
I hope you understand my problem with the indexing, maybe you have a solution for this.

Thx,
Joe.

 

[gloin]

HI :barresed:

i'm trying to do the following thing:

Signal arr: std_logic_vector(1 downto 0);
Signal BitPos: integer:=0;

process(CLK)
begin

arr(BitPos) <= Din; --Din is std_logic type
BitPos <= BitPos + 1;

end process;

I'm trying to run a TestBench in which Din is set to '0' initialy and to '1' after 10ns. Now I understand how the process works and that BitPos is actually set to 1 before Din is inserted to arr, which means Din is inserted to arr(1) insted of arr(0). All i want to do is instering the first Din into arr(0) and the second Din into arr(1).
I hope you understand my problem with the indexing, maybe you have a solution for this.

Thx,
Joe.

you wrote your code without a process,you know this code will run concurrently. So if you want sequential run you should write it in a process.

process(clk)
begin
if clk'event and clk = '1' then
arr(BitPos) <= Din; --Din is std_logic type
BitPos <= BitPos + 1;
.
.
.
.
end if;
end process;

hope it helps..

regards,
Gloin