newb: generic vector

Discussion in 'VHDL' started by Pela, Jan 22, 2005.

  1. Pela

    Pela Guest

    If I have a logic vector like this (4 bits):
    signal s: std_logic_vector(3 downto 0);
    I can assign a zero value this way:
    s <= "0000";

    How can I assign zero if vector size is generic? Do I need a FOR loop?
    signal s: std_logic_vector(N-1 downto 0);
    s <= ???

    TIA

    --
    Pela
     
    Pela, Jan 22, 2005
    #1
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  2. Le Sat, 22 Jan 2005 18:31:44 +0000, Pela a écrit :

    > If I have a logic vector like this (4 bits):
    > signal s: std_logic_vector(3 downto 0);
    > I can assign a zero value this way:
    > s <= "0000";
    >
    > How can I assign zero if vector size is generic? Do I need a FOR loop?
    > signal s: std_logic_vector(N-1 downto 0);
    > s <= ???
    >
    > TIA


    s <= (others=>'0');

    JC
     
    Jean-Christophe Le Lann, Jan 22, 2005
    #2
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