i wrote some code for loadable shift register..
library ieee;
use ieee.std_logic_1164.all;
entity loadable_shift_register is
generic(
DATA_WIDTH : natural := 12);
port(
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
ld : in std_logic;
clk : in std_logic;
rsh : in std_logic;
rst_L : in std_logic;
data_out: out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity loadable_shift_register;
architecture bhv of loadable_shift_register is
begin
process (clk, rst_L, ld, data_in, rsh)
variable data : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
if rst_L = '0' then
data := (others => '0');
elseif c'event and clk = '1' then
if rsh = '1' then
for i in 0 to (DATA_WIDTH-1) loop
data(i) := data(i+1);
end loop;
elseif ld = '1' then
data := data_in;
end if;
else
data := data;
end if;
data_out <= data;
end process;
end architecture bhv;
-------------------------------------------------------------------------------
-- TEST BENCH FOR LOADABLE SHIFT REGISTER
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity loadable_shift_register_tben is
end loadable_shift_register_tben;
architecture tben of loadable_shift_register_tben is
component loadable_shift_register
generic (
DATA_WIDTH : natural);
port (
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
ld : in std_logic;
rsh : in std_logic;
clk : in std_logic;
rst_L : in std_logic;
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal data_in : std_logic_vector(11 downto 0) := "000000000000";
signal ld : std_logic := '0';
signal rsh : std_logic := '0';
signal clk : std_logic := '0';
signal rst_L : std_logic := '0';
signal data_out : std_logic_vector(11 downto 0);
begin -- tben
-- Instantiation of device under test
DUT : loadable_shift_register
generic map (DATA_WIDTH => 12)
port map (data_in => data_in,
ld => ld,
rsh => rsh,
clk => clk,
rst_L => rst_L,
data_out => data_out);
-- DUT stimulus
-- generates a periodic clock with T_clk = 40 ns
process
begin -- process clk_gen
wait for 20 ns;
clk <= not(clk);
end process;
-- models the reset signal (starts at '0')
rst_L <= '1' after 15 ns;
-- models the signals data_in, ld and rsh for each period of clk
process (clk, rst_L)
variable clk_ticks : natural := 0; -- keeps track of number of clk ticks
begin -- process
if rst_L = '0' then -- asynchronous reset (active low)
clk_ticks := 0;
data_in <= "000000000000" after 5 ns;
ld <= '0' after 5 ns;
rsh <= '0' after 5 ns;
elsif clk'event and clk = '1' then -- rising clock edge
clk_ticks := clk_ticks+1;
if clk_ticks = 1 then
data_in <= "000011110000" after 5 ns;
ld <= '1' after 5 ns;
rsh <= '0' after 5 ns;
elsif clk_ticks = 2 then
data_in <= "111111111111" after 5 ns;
ld <= '0' after 5 ns;
rsh <= '0' after 5 ns;
elsif clk_ticks = 3 then
data_in <= "111111111111" after 5 ns;
ld <= '0' after 5 ns;
rsh <= '1' after 5 ns;
elsif clk_ticks = 4 then
data_in <= "111111111111" after 5 ns;
ld <= '1' after 5 ns;
rsh <= '1' after 5 ns;
elsif clk_ticks = 5 then
data_in <= "111111111111" after 5 ns;
ld <= '1' after 5 ns;
rsh <= '0' after 5 ns;
else
data_in <= "XXXXXXXXXXXX" after 5 ns;
ld <= '0' after 5 ns;
rsh <= '0' after 5 ns;
end if;
end if;
end process;
end tben;
but when i compile i had follewing errow message..
# ** Error: D:/lowpassfilter/loadable_shift_register.vhd(67): near "c": expecting: <= :=
# ** Error: D:/lowpassfilter/loadable_shift_register.vhd(67): near "and": expecting: <= :=
# ** Error: D:/lowpassfilter/loadable_shift_register.vhd(72): near "ld": expecting: <= :=
please give me some hints...
library ieee;
use ieee.std_logic_1164.all;
entity loadable_shift_register is
generic(
DATA_WIDTH : natural := 12);
port(
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
ld : in std_logic;
clk : in std_logic;
rsh : in std_logic;
rst_L : in std_logic;
data_out: out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity loadable_shift_register;
architecture bhv of loadable_shift_register is
begin
process (clk, rst_L, ld, data_in, rsh)
variable data : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
if rst_L = '0' then
data := (others => '0');
elseif c'event and clk = '1' then
if rsh = '1' then
for i in 0 to (DATA_WIDTH-1) loop
data(i) := data(i+1);
end loop;
elseif ld = '1' then
data := data_in;
end if;
else
data := data;
end if;
data_out <= data;
end process;
end architecture bhv;
-------------------------------------------------------------------------------
-- TEST BENCH FOR LOADABLE SHIFT REGISTER
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity loadable_shift_register_tben is
end loadable_shift_register_tben;
architecture tben of loadable_shift_register_tben is
component loadable_shift_register
generic (
DATA_WIDTH : natural);
port (
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
ld : in std_logic;
rsh : in std_logic;
clk : in std_logic;
rst_L : in std_logic;
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal data_in : std_logic_vector(11 downto 0) := "000000000000";
signal ld : std_logic := '0';
signal rsh : std_logic := '0';
signal clk : std_logic := '0';
signal rst_L : std_logic := '0';
signal data_out : std_logic_vector(11 downto 0);
begin -- tben
-- Instantiation of device under test
DUT : loadable_shift_register
generic map (DATA_WIDTH => 12)
port map (data_in => data_in,
ld => ld,
rsh => rsh,
clk => clk,
rst_L => rst_L,
data_out => data_out);
-- DUT stimulus
-- generates a periodic clock with T_clk = 40 ns
process
begin -- process clk_gen
wait for 20 ns;
clk <= not(clk);
end process;
-- models the reset signal (starts at '0')
rst_L <= '1' after 15 ns;
-- models the signals data_in, ld and rsh for each period of clk
process (clk, rst_L)
variable clk_ticks : natural := 0; -- keeps track of number of clk ticks
begin -- process
if rst_L = '0' then -- asynchronous reset (active low)
clk_ticks := 0;
data_in <= "000000000000" after 5 ns;
ld <= '0' after 5 ns;
rsh <= '0' after 5 ns;
elsif clk'event and clk = '1' then -- rising clock edge
clk_ticks := clk_ticks+1;
if clk_ticks = 1 then
data_in <= "000011110000" after 5 ns;
ld <= '1' after 5 ns;
rsh <= '0' after 5 ns;
elsif clk_ticks = 2 then
data_in <= "111111111111" after 5 ns;
ld <= '0' after 5 ns;
rsh <= '0' after 5 ns;
elsif clk_ticks = 3 then
data_in <= "111111111111" after 5 ns;
ld <= '0' after 5 ns;
rsh <= '1' after 5 ns;
elsif clk_ticks = 4 then
data_in <= "111111111111" after 5 ns;
ld <= '1' after 5 ns;
rsh <= '1' after 5 ns;
elsif clk_ticks = 5 then
data_in <= "111111111111" after 5 ns;
ld <= '1' after 5 ns;
rsh <= '0' after 5 ns;
else
data_in <= "XXXXXXXXXXXX" after 5 ns;
ld <= '0' after 5 ns;
rsh <= '0' after 5 ns;
end if;
end if;
end process;
end tben;
but when i compile i had follewing errow message..
# ** Error: D:/lowpassfilter/loadable_shift_register.vhd(67): near "c": expecting: <= :=
# ** Error: D:/lowpassfilter/loadable_shift_register.vhd(67): near "and": expecting: <= :=
# ** Error: D:/lowpassfilter/loadable_shift_register.vhd(72): near "ld": expecting: <= :=
please give me some hints...