newbie needs some helps....

Discussion in 'VHDL' started by zhfs, Apr 16, 2009.

  1. zhfs

    zhfs

    Joined:
    Apr 16, 2009
    Messages:
    1
    i wrote some code for loadable shift register..

    library ieee;
    use ieee.std_logic_1164.all;

    entity loadable_shift_register is
    generic(
    DATA_WIDTH : natural := 12);
    port(
    data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
    ld : in std_logic;
    clk : in std_logic;
    rsh : in std_logic;
    rst_L : in std_logic;
    data_out: out std_logic_vector(DATA_WIDTH-1 downto 0));
    end entity loadable_shift_register;

    architecture bhv of loadable_shift_register is
    begin
    process (clk, rst_L, ld, data_in, rsh)
    variable data : std_logic_vector(DATA_WIDTH-1 downto 0);
    begin
    if rst_L = '0' then
    data := (others => '0');
    elseif c'event and clk = '1' then
    if rsh = '1' then
    for i in 0 to (DATA_WIDTH-1) loop
    data(i) := data(i+1);
    end loop;
    elseif ld = '1' then
    data := data_in;
    end if;
    else
    data := data;

    end if;


    data_out <= data;

    end process;

    end architecture bhv;



    -------------------------------------------------------------------------------
    -- TEST BENCH FOR LOADABLE SHIFT REGISTER
    -------------------------------------------------------------------------------

    library ieee;
    use ieee.std_logic_1164.all;

    entity loadable_shift_register_tben is
    end loadable_shift_register_tben;

    architecture tben of loadable_shift_register_tben is

    component loadable_shift_register
    generic (
    DATA_WIDTH : natural);
    port (
    data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
    ld : in std_logic;
    rsh : in std_logic;
    clk : in std_logic;
    rst_L : in std_logic;
    data_out : out std_logic_vector(DATA_WIDTH-1 downto 0));
    end component;

    signal data_in : std_logic_vector(11 downto 0) := "000000000000";
    signal ld : std_logic := '0';
    signal rsh : std_logic := '0';
    signal clk : std_logic := '0';
    signal rst_L : std_logic := '0';
    signal data_out : std_logic_vector(11 downto 0);

    begin -- tben

    -- Instantiation of device under test
    DUT : loadable_shift_register
    generic map (DATA_WIDTH => 12)
    port map (data_in => data_in,
    ld => ld,
    rsh => rsh,
    clk => clk,
    rst_L => rst_L,
    data_out => data_out);

    -- DUT stimulus

    -- generates a periodic clock with T_clk = 40 ns
    process
    begin -- process clk_gen
    wait for 20 ns;
    clk <= not(clk);
    end process;

    -- models the reset signal (starts at '0')
    rst_L <= '1' after 15 ns;

    -- models the signals data_in, ld and rsh for each period of clk
    process (clk, rst_L)
    variable clk_ticks : natural := 0; -- keeps track of number of clk ticks
    begin -- process
    if rst_L = '0' then -- asynchronous reset (active low)
    clk_ticks := 0;
    data_in <= "000000000000" after 5 ns;
    ld <= '0' after 5 ns;
    rsh <= '0' after 5 ns;
    elsif clk'event and clk = '1' then -- rising clock edge
    clk_ticks := clk_ticks+1;
    if clk_ticks = 1 then
    data_in <= "000011110000" after 5 ns;
    ld <= '1' after 5 ns;
    rsh <= '0' after 5 ns;
    elsif clk_ticks = 2 then
    data_in <= "111111111111" after 5 ns;
    ld <= '0' after 5 ns;
    rsh <= '0' after 5 ns;
    elsif clk_ticks = 3 then
    data_in <= "111111111111" after 5 ns;
    ld <= '0' after 5 ns;
    rsh <= '1' after 5 ns;
    elsif clk_ticks = 4 then
    data_in <= "111111111111" after 5 ns;
    ld <= '1' after 5 ns;
    rsh <= '1' after 5 ns;
    elsif clk_ticks = 5 then
    data_in <= "111111111111" after 5 ns;
    ld <= '1' after 5 ns;
    rsh <= '0' after 5 ns;
    else
    data_in <= "XXXXXXXXXXXX" after 5 ns;
    ld <= '0' after 5 ns;
    rsh <= '0' after 5 ns;
    end if;
    end if;
    end process;

    end tben;


    but when i compile i had follewing errow message..

    # ** Error: D:/lowpassfilter/loadable_shift_register.vhd(67): near "c": expecting: <= :=
    # ** Error: D:/lowpassfilter/loadable_shift_register.vhd(67): near "and": expecting: <= :=
    # ** Error: D:/lowpassfilter/loadable_shift_register.vhd(72): near "ld": expecting: <= :=

    please give me some hints...
     
    zhfs, Apr 16, 2009
    #1
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  2. zhfs

    GeorgSchmalz

    Joined:
    Apr 15, 2009
    Messages:
    1
    Use elsif instead of elseif.
     
    GeorgSchmalz, Apr 16, 2009
    #2
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  3. zhfs

    surpriya.7

    Joined:
    Mar 24, 2009
    Messages:
    5
    Hi zhfs,
    i think your code is not showing the errors you are saying it gets...rather im getting a diff set of errors...

    Compiling vhdl file "D:/Projects/codes/sample codes/trial/try2.vhd" in Library work.
    ERROR:HDLParsers:3313 - "D:/Projects/codes/sample codes/trial/try2.vhd" Line 23. Undefined symbol 'elseif'. Should it be: 'else if' or elsif?
    ERROR:HDLParsers:1209 - "D:/Projects/codes/sample codes/trial/try2.vhd" Line 23. elseif: Undefined symbol (last report in this block)
    ERROR:HDLParsers:164 - "D:/Projects/codes/sample codes/trial/try2.vhd" Line 23. parse error, unexpected IDENTIFIER, expecting OPENPAR or TICK or LSQBRACK
    ERROR:HDLParsers:164 - "D:/Projects/codes/sample codes/trial/try2.vhd" Line 31. parse error, unexpected ELSE, expecting END

    Process "Check Syntax" failed

    use of elsif instead of elseif is one correction like GeorgSchmalz mentioned...

    although i would suggest that you should avoid the use of if-else statements if you are space consious on your selected device. but since you are in some initial stages of coding, you may just enjoy experimenting more with the statements and syntax.... happy coding
     
    surpriya.7, Apr 16, 2009
    #3
  4. zhfs

    cheevu

    Joined:
    Jan 9, 2008
    Messages:
    5
    Location:
    BAngalore

    i think u r using c instead of clk..
     
    cheevu, Apr 17, 2009
    #4
  5. zhfs

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    A couple of things for a newbie:

    "# ** Error: D:/lowpassfilter/loadable_shift_register.vhd(67): near "c": expecting: <= :="

    The number in parenthesis is the line number where the compiler detected the problem. It is typically an issue with a line just before the one reported. If you don't have an editor that shows line numbers, get one! I like Crimson Editor. emacs is very popular because it has lots of built in VHDL features.

    As stated in the earlier responses, the errors appear to be in your architecture definition, not in your test bench.

    John
     
    JohnDuq, Apr 17, 2009
    #5
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