newbie question about <= and :=? what's the difference?

Discussion in 'VHDL' started by walala, Sep 3, 2003.

  1. walala

    walala Guest

    Dear all,

    The discussion about <= and := is in all books about VHDL. But after
    reading a lot, I am still not very clear about the difference...

    For example, if I have a input X multiply with a constant coefficient
    a, temp=a*X

    I hope to store this aX term for later use. In fact, later I will need

    Y(1)=temp,

    Y(2)=2*temp,

    Y(3)=-temp,

    What do I write? Do I use temp<=a*X or temp:=a*X? what is the
    difference?

    Please help me! Thanks a lot,

    -Walala
    walala, Sep 3, 2003
    #1
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  2. > The discussion about <= and := is in all books about VHDL. But after
    > reading a lot, I am still not very clear about the difference...


    There are two types of 'storage' in VHDL: signals and variables. Variables
    get their value immediately. Signals get their value after a delta delay.
    Variables get a value assigned using :=. Signals get their value assigned
    using <=.

    Hope this helps. :)

    Regards,

    Pieter Hulshoff
    Pieter Hulshoff, Sep 4, 2003
    #2
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  3. walala

    walala Guest

    Dear Pieter,

    Thanks for your answer. However, every book says that there are two kind of
    "storage", one is signal(with delay) and another is variable(not delay), but
    what does it related to synthesized circuit?

    What do they map to? Variable synthesize to wire, signal synthesize to
    flip-flop?

    Am I right?

    > For example, if I have a input X multiply with a constant coefficient
    > a, temp=a*X
    >
    > I hope to store this aX term for later use. In fact, later I will need
    >
    > Y(1)=temp,
    >
    > Y(2)=2*temp,
    >
    > Y(3)=-temp,
    >
    > What do I write? Do I use temp<=a*X or temp:=a*X? what is the
    > difference?


    -Walala

    "walala" <> wrote in message
    news:...
    > Dear all,
    >
    > The discussion about <= and := is in all books about VHDL. But after
    > reading a lot, I am still not very clear about the difference...
    >
    > For example, if I have a input X multiply with a constant coefficient
    > a, temp=a*X
    >
    > I hope to store this aX term for later use. In fact, later I will need
    >
    > Y(1)=temp,
    >
    > Y(2)=2*temp,
    >
    > Y(3)=-temp,
    >
    > What do I write? Do I use temp<=a*X or temp:=a*X? what is the
    > difference?
    >
    > Please help me! Thanks a lot,
    >
    > -Walala

    "Pieter Hulshoff" <> wrote in message
    news:3f56c0a1$0$49098$4all.nl...
    > > The discussion about <= and := is in all books about VHDL. But after
    > > reading a lot, I am still not very clear about the difference...

    >
    > There are two types of 'storage' in VHDL: signals and variables. Variables
    > get their value immediately. Signals get their value after a delta delay.
    > Variables get a value assigned using :=. Signals get their value assigned
    > using <=.
    >
    > Hope this helps. :)
    >
    > Regards,
    >
    > Pieter Hulshoff
    >
    walala, Sep 4, 2003
    #3
  4. Variables can also map to FF's and signals to wires ...

    Let me explain a little (and thus incomplete) the background of
    signals and varaibles.
    VHDL is not a 'sequential language', e.g. concurrent statements
    can execute at the same time. However on my INTEL platform
    these concurrent statements are executed sequentially!
    Concurrent statements can only communicatie with each
    others using SIGNALS. The simulation cycle of VHDL has
    two stages:
    - execute processes (SIGNALS VALUES do ot change)
    - update signals (if necessary)
    Due to this mechanism concurrent statements can be in any order
    in the description whereas the simulation behavior remains the same.
    This also explains why SIGNALS are declared in the the
    declaration area of the ARCHITECTURE (and some other
    places, e.g. ENTITY).
    VARIABLE are like variables in other languages. They can only
    be declared within a SEQUENTIAL piece of code, e.g.
    process, function procedure (forget 'shared variable') and therefore
    can not be used for communication with other concurrent statements.
    As Pieter already mentioned, variables are always updated
    immediatly.

    PROCESS(reset,clk)
    VARIBALE count : INTEGER;
    BEGIN
    IF reset='0' THEN
    counter := 0; ten<=false;
    ELSIF rising_edge(clk) THEN
    IF d='1' THEN counter:= counter+1; END IF;
    ten <= counter=10;
    END IF;
    END PROCESS;

    Variables can map to FF's. Have a look at the previous description.
    After each rising edge of the clock the counter value is incremented
    if d is '1'. In this case the variable counter must be remembered, and
    indeed your synthesis tool will use a FFs for this variable.
    If a variable is always assigned a value BEFORE it is read the
    synthesis tool will not use FF's.
    The counter value is updated immediatly, e.g. after execution of
    counter:= counter+1
    counter is incremented immediatly (like in most programming languages)

    PROCESS(reset,clk)
    VARIBALE count : INTEGER;
    BEGIN
    IF reset='0' THEN
    ...
    ELSIF rising_edge(clk) THEN
    b <= a;
    c <= b;

    Lets have a look at signals. In the description above SIGNAL b get the
    value of a, and next the statement is executed that c gets the value of b.
    BUT!!! remember signal values are frozen during execution (=
    are never updated immediatly). That means that after execution of
    b <= a;
    b remains it (old) value. The update of signal b occurs after all concurrent
    statements are finished (after a delta delay).
    That means that the statement
    c <= b;
    wil NOT use the value of a. Indeed this looks like a delay line. After
    2 active clock edges signal c will have the value of a.
    perform a simulation!, and indeed your synthesis tool will also
    map this to a cascade of two FFs.

    Hope this helps,

    Egbert Molenkamp



    "walala" <> wrote in message
    news:bj6jm5$a80$...
    > Dear Pieter,
    >
    > Thanks for your answer. However, every book says that there are two kind

    of
    > "storage", one is signal(with delay) and another is variable(not delay),

    but
    > what does it related to synthesized circuit?
    >
    > What do they map to? Variable synthesize to wire, signal synthesize to
    > flip-flop?
    >
    > Am I right?
    >
    > > For example, if I have a input X multiply with a constant coefficient
    > > a, temp=a*X
    > >
    > > I hope to store this aX term for later use. In fact, later I will need
    > >
    > > Y(1)=temp,
    > >
    > > Y(2)=2*temp,
    > >
    > > Y(3)=-temp,
    > >
    > > What do I write? Do I use temp<=a*X or temp:=a*X? what is the
    > > difference?

    >
    > -Walala
    >
    > "walala" <> wrote in message
    > news:...
    > > Dear all,
    > >
    > > The discussion about <= and := is in all books about VHDL. But after
    > > reading a lot, I am still not very clear about the difference...
    > >
    > > For example, if I have a input X multiply with a constant coefficient
    > > a, temp=a*X
    > >
    > > I hope to store this aX term for later use. In fact, later I will need
    > >
    > > Y(1)=temp,
    > >
    > > Y(2)=2*temp,
    > >
    > > Y(3)=-temp,
    > >
    > > What do I write? Do I use temp<=a*X or temp:=a*X? what is the
    > > difference?
    > >
    > > Please help me! Thanks a lot,
    > >
    > > -Walala

    > "Pieter Hulshoff" <> wrote in message
    > news:3f56c0a1$0$49098$4all.nl...
    > > > The discussion about <= and := is in all books about VHDL. But after
    > > > reading a lot, I am still not very clear about the difference...

    > >
    > > There are two types of 'storage' in VHDL: signals and variables.

    Variables
    > > get their value immediately. Signals get their value after a delta

    delay.
    > > Variables get a value assigned using :=. Signals get their value

    assigned
    > > using <=.
    > >
    > > Hope this helps. :)
    > >
    > > Regards,
    > >
    > > Pieter Hulshoff
    > >

    >
    >
    Egbert Molenkamp, Sep 4, 2003
    #4
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