Newbie question about first project.

[Mike Deblis]

Hi,

Be gentle, please! I've started reading "The Student's Guide to VHDL" and
have puchased a CoolRunner II Development Kit from Xilinx (very nice and
reasonably priced) - the kit gave me all the s/w I think I'll need for a
while, though the manual is rubbish, hence the book. Book seems very good -
accessible and easy to use - about half way through now - I program
professionally anyway, and have an EE background, so its not too tough
(quite fun actually...).

Now, I know very little about this subject, but I like making clocks... Is a
digital alarm clock (7 seg LEDs or other display technology) a reasonable
project to start out with? Normally I'd have done this with a PIC or AVR,
but it occurred to me that using a CPLD would be... well... different....

But is it sensible? I would appreciate any comments on this approach,
preferably helpful ;-)

BTW. This is *not* a student project - my student days were about 25 years
ago, hence my having "fun" learning different stuff...

Many thanks

Mike

 

[Tim Hubberstey]

Now, I know very little about this subject, but I like making clocks... Is a
digital alarm clock (7 seg LEDs or other display technology) a reasonable
project to start out with? Normally I'd have done this with a PIC or AVR,
but it occurred to me that using a CPLD would be... well... different....

This is off-topic for this group, but I'll answer anyway, just this
once. In future, implementation questions like these are better posted
to comp.arch.fpga.

As a VHDL project, this is a very reasonable first project. However,
depending on the size of the CPLDs included in your dev. kit, this is
either fairly easy, difficult, or impossible in a CPLD.

CPLDs have a very limited number of flip-flops available (the number of
FFs is given by the macrocell count). You will need at least 20 FFs for
counters for the time. Assuming a 32768 Hz crystal for the clock, you
will need 15 FFs to divide this down to 1 Hz. You will need at least 14
FFs for the alarm register. Multiplexing a 7-segment display will
require at least 17 FFs. That is a minimum of 66 FFs for a
straightforward design. There are tricks you can use to reduce this
number but they will only save a few FFs at the expense of significant
complexity. This means you need to have at least an X2C256 or XCR3128XL
available in your kit before you should even consider trying this. If
you use 60 Hz as your clock (6 FFs instead of 14 for the divider), you
MIGHT be able to squeeze it into a 64-macrocell device.

 

[Mike Deblis]

different....

This is off-topic for this group, but I'll answer anyway, just this
once. In future, implementation questions like these are better posted
to comp.arch.fpga.

Sorry about that, I'll repost there...

As a VHDL project, this is a very reasonable first project. However,
depending on the size of the CPLDs included in your dev. kit, this is
either fairly easy, difficult, or impossible in a CPLD.

[... snip ...]

I think the kit uses an X2C256, so I may be OK there. I really appreciate
your comments and I'll try in the correct group.

Thanks again,

Mike