newbie vhdl question on variable length of '1'

Discussion in 'VHDL' started by Carson, Oct 2, 2005.

  1. Carson

    Carson Guest

    hi

    is there a way (or function) in vhdl such that I can specify a
    variable length of '1' easily?

    Thanks,

    Carson
     
    Carson, Oct 2, 2005
    #1
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  2. Carson

    john Doef Guest

    Carson a écrit :

    > hi
    >
    > is there a way (or function) in vhdl such that I can specify a
    > variable length of '1' easily?

    Hello,

    your question is really confusing.
    What do you mean by 'specify a variable length' ?
    What do you mean by '1' ? The number one or a bit '1' ?

    In VHDL, you must declare variables with their type.
    eg:
    variable v1 : std_logic; -- a variable containing one bit
    variable v8 : std_logic_vector (7 downto 0); -- a variable
    containing 8 bits.

    JD.
     
    john Doef, Oct 3, 2005
    #2
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  3. Carson wrote:

    > is there a way (or function) in vhdl such that I can specify a
    > variable length of '1' easily?


    Do you mean "0000...00001" ?

    std_logic_vector(conv_unsigned(1,N))

    or "1111....1111"?

    std_logic_vector(conv_signed(-1,N))

    Regards,
    Mark
     
    Mark McDougall, Oct 4, 2005
    #3
  4. Carson

    Carson Guest

    Hi Mark,

    it works! Thanks!

    Carson
     
    Carson, Oct 4, 2005
    #4
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