[NEWBIE] What's wrong in this code?!

Discussion in 'VHDL' started by Marco Pikiri, Jan 3, 2005.

  1. Marco Pikiri

    Marco Pikiri Guest

    Hi all.

    I use Altera Max Plus II for an "EPF10K70RC240-4" device.

    Here the code:

    **************
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;

    entity progetto2 is

    port(clock_25MHz, pb1, pb2 : in std_logic;

    segment_a, segment_b, segment_c,
    segment_d, segment_e,
    segment_f, segment_g : out std_logic;

    segment_a1, segment_b1, segment_c1,
    segment_d1, segment_e1,
    segment_f1, segment_g1 : out std_logic;

    punto, punto1 : out std_logic);

    end progetto2;

    architecture unica of progetto2 is

    -- dichiarazione segnali globali
    signal clock_10hz : std_logic;
    signal ingresso : std_logic; -- onda quadra in ingresso
    signal uscita : std_logic; -- onda quadra in uscita
    signal led_u, led_d : integer range 0 to 9;
    signal segment_data, segment_data1 : std_logic_vector(6 downto 0);
    signal freq_in : integer range 10000 to 200000;
    signal divisore : integer := (led_d*10 + led_u);
    signal freq_out : integer := (freq_in mod divisore);

    begin

    -- Creo il clock a 10 Hz, necessario per capire se i pulsanti vengono
    premuti per più o meno di 100 ms
    clock: PROCESS

    VARIABLE count_10hz : integer range 0 to 1258750;

    begin

    wait until clock_25MHz'EVENT and clock_25MHz = '1';

    if count_10hz /= 1258749 then
    count_10hz := count_10hz + 1;

    else
    count_10hz := 0;
    clock_10hz <= NOT clock_10hz;

    end if;

    end process;


    -- creazione del contatore 1 -> 99
    contatore: PROCESS

    VARIABLE cnt : integer range 0 to 10;

    begin

    wait until (clock_10hz'event and clock_10hz = '1');

    if (pb1 = '0' and pb2 = '0') then -- condizione di reset

    if cnt /= 10 then
    cnt := cnt + 1;

    else
    cnt := 0;
    led_u <= 1;
    led_d <= 0;

    end if;

    elsif (pb1 = '0') then -- incremento contatore

    if (led_u = 9 and led_d /=9) then -- led unità a fondo scala e led
    decine no
    led_u <= 0;
    led_d <= led_d + 1;

    elsif (led_u = 9 and led_d = 9) then -- led unità e led decine a fondo
    scala (9)
    led_u <= 1;
    led_d <= 0;

    else -- né led unità né led decine a fondo scala
    led_u <= led_u + 1;

    end if;

    elsif (pb2 = '0') then -- decremento contatore

    if (led_u = 0 and led_d /= 0) then -- led unità a inizio scala e led
    decine no
    led_u <= 9;
    led_d <= led_d - 1;

    elsif (led_u = 0 and led_d = 0) then -- led unità e led decine a inizio
    scala (0)
    led_u <= 9;
    led_d <= 9;

    elsif (led_u = 1 and led_d = 0) then -- salto di 00
    led_u <= 9;
    led_d <= 9;

    else -- né led unità né led decine a inizio scala
    led_u <= led_u - 1;

    end if;

    else

    led_d <= led_d;
    led_u <= led_u;

    end if;

    end process;

    -- i due processi seguenti sono per verificare il corretto funzionamento del
    contatore

    decine : PROCESS (led_d)

    begin

    case led_d is

    when 0 => segment_data <= "1111110";
    when 1 => segment_data <= "0110000";
    when 2 => segment_data <= "1101101";
    when 3 => segment_data <= "1111001";
    when 4 => segment_data <= "0110011";
    when 5 => segment_data <= "1011011";
    when 6 => segment_data <= "1011111";
    when 7 => segment_data <= "1110000";
    when 8 => segment_data <= "1111111";
    when 9 => segment_data <= "1111011";
    when others => segment_data <= "0000101"; -- Er (Errore)


    end case;

    segment_a <= NOT segment_data(6);
    segment_b <= NOT segment_data(5);
    segment_c <= NOT segment_data(4);
    segment_d <= NOT segment_data(3);
    segment_e <= NOT segment_data(2);
    segment_f <= NOT segment_data(1);
    segment_g <= NOT segment_data(0);

    punto <= '1';

    end process;

    unità : PROCESS (led_u)

    begin

    case led_u is

    when 0 => segment_data1 <= "0000001";
    when 1 => segment_data1 <= "1001111";
    when 2 => segment_data1 <= "0010010";
    when 3 => segment_data1 <= "0000110";
    when 4 => segment_data1 <= "1001100";
    when 5 => segment_data1 <= "0100100";
    when 6 => segment_data1 <= "0100000";
    when 7 => segment_data1 <= "0001111";
    when 8 => segment_data1 <= "0000000";
    when 9 => segment_data1 <= "0000100";
    when others => segment_data1 <= "0000101"; -- Er (Errore)


    end case;

    segment_a1 <= segment_data1(6);
    segment_b1 <= segment_data1(5);
    segment_c1 <= segment_data1(4);
    segment_d1 <= segment_data1(3);
    segment_e1 <= segment_data1(2);
    segment_f1 <= segment_data1(1);
    segment_g1 <= segment_data1(0);

    punto1 <= '1';

    end process;

    -- Creo il segnale di onda quadra (livelli logici 0 - 1) alla frequenza
    "freq_in" desiderata (compresa tra 10 e 200 KHz)

    segnale_in : PROCESS

    VARIABLE max_count_in : integer := ((25175000) mod (2*freq_in));
    VARIABLE count_in : integer;

    begin

    wait until clock_25MHz'EVENT and clock_25MHz = '1';

    if count_in /= (max_count_in-1) then
    count_in := count_in + 1;

    else
    count_in := 0;
    ingresso <= NOT ingresso;

    end if;

    end process;

    segnale_out : PROCESS

    VARIABLE max_count_out : integer := ((25175000) mod (2*freq_out));
    VARIABLE count_out : integer;

    begin

    wait until clock_25MHz'EVENT and clock_25MHz = '1';

    if count_out /= (max_count_out-1) then
    count_out := count_out + 1;

    else
    count_out := 0;
    uscita <= NOT uscita;

    end if;

    end process;

    end unica;
    **************

    Going to "Save & Check" is all ok, but "Save & Compile" notify 64 errors for
    "missing source" on variables "max_count_in" (32 errors) and "max_count_out"
    (the other 32 errors). As a newbie, I ignore what's the problem's type...
    For me the syntax's code is ok.

    Anyone can help me, please?

    Many thanks.

    --
    Marco Pikiri
    Marco Pikiri, Jan 3, 2005
    #1
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  2. Marco Pikiri a écrit :

    > Going to "Save & Check" is all ok, but "Save & Compile" notify 64 errors for
    > "missing source" on variables "max_count_in" (32 errors) and "max_count_out"
    > (the other 32 errors). As a newbie, I ignore what's the problem's type...
    > For me the syntax's code is ok.


    You declare max_count_in as a variable but you never assign a value,
    except at declaration where you assign a default value based on a
    signal's value, and you never even assign a value to this signal (freq_in)
    Same goes for max_count_out.
    Consider using generics and constants.

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
    Nicolas Matringe, Jan 3, 2005
    #2
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  3. Marco Pikiri

    Tim Good Guest

    Hi,

    VHDL was originally developed as a way to write specifications for
    complex digital designs. This was quite some time prior to the tools
    for synthesis came along.

    You should find that there is only a sub-set of valid VHDL syntax which
    will work with your modelling tool (i.e. behavioral description level).
    From this an even smaller fraction of the possible VHDL statements
    will actually produce synthesisable code.

    There are many textbooks which describe the VHDL language and a smaller
    number which describe SYNTHESIS using VHDL. I wont recommend a
    particular text as there are numerous to choose from and it is a matter
    of personal taste which authors writing style you like the most. You
    may find it useful to read one or two of the books on synthesis to get
    some idea of the coding styles used for reliable synthesis and a level
    of description called Register Transfer Level (RTL). I am assuming that
    as you are quoting a device part number you are seeking a synthesisable
    description.

    From a quick look at your code here are a few observations you should
    find helpful:

    1. The 2x32 errors arrise from your two integer (32-bit) variables
    "max_count_in" and "max_count_out", the problem is that these have no
    initial value. But this is not an end to the problem...

    2. The style of coding you are using (wait statements, integers, etc) is
    just fine for a behavioural model but I guess you are finding synthesis
    difficult. Suggest you need to change programming style a little for
    synthesis to work.

    (a) use "if clk'event and clk='1'" rather than "wait until "

    (b) use "std_logic_vector( Nbits-1 downto 0)" rather than integer where
    Nbits is the number of bits you really want.

    (c) create a reset signal and use it to force a stable initial state
    for each counter, example process:

    if reset='1' then
    counter<=0;
    else
    if clk'event and clk='1' then
    counter<=counter+1;
    end if; -- no else to infer register behaviour
    end if

    (d) look at some examples of code eg www.opencores.org

    Hope this helps,


    Tim
    Tim Good, Jan 3, 2005
    #3
  4. Marco Pikiri

    Marco Pikiri Guest

    Nicolas Matringe wrote:

    > You declare max_count_in as a variable but you never assign a value,
    > except at declaration where you assign a default value based on a
    > signal's value, and you never even assign a value to this signal
    > (freq_in) Same goes for max_count_out.
    > Consider using generics and constants.


    Thanks a lot!

    --
    Marco
    Marco Pikiri, Jan 3, 2005
    #4
  5. Marco Pikiri

    Marco Pikiri Guest

    Tim Good wrote:

    > 1. [CUT]
    > 2. [CUT]


    > Hope this helps,


    Surely :)

    Thanks a lot!
    --
    Marco
    Marco Pikiri, Jan 3, 2005
    #5
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