NEXYS2 Board from Digilent

Discussion in 'VHDL' started by mmishra, Jun 29, 2009.

  1. mmishra

    mmishra

    Joined:
    Jun 10, 2009
    Messages:
    3
    Hello,

    I have a question regarding the EPP-like interface that connects the on-board USB Controller to the Design in the FPGA (Spartan 3E), on the NEXYS2 board from Digilent.

    1) Are the signals such as EppAddrStrb, EppDataStrb, EppWr etc. that go from the USB Controller into the FPGA, synchronous to the System Clock (50 MHz, B8 pin on FPGA) or to the USB Clk (48 MHz, T15 pin on the FPGA) ?

    2) What would be an appopriate mechanism to generate a synchronously-deasserted Reset signal for the design inside the FPGA ?

    Thanks a lot,

    Manoj
     
    mmishra, Jun 29, 2009
    #1
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