Nice clean pulse signal

Discussion in 'VHDL' started by matchstick86, Dec 14, 2009.

  1. matchstick86

    matchstick86

    Joined:
    Oct 2, 2009
    Messages:
    19
    Let's say we have a signal as such, so I have a sig_reg to make a delay of the signal by half clock cycle.

    And using this code:
    Code:
    process(clk, sig, sig_reg) is
    begin
    	if rising_edge(clk) then
    		sig_reg <= sig;
    	end if;
    		sig_pulse<=sig and not (sig_reg);
    end process;
    
    Code:
    Sig: 
    ....----............---........----............------....---.......
    
    Sig_reg:
    ......----............---........----............------....---.....
    
    Sig_pulse (final result):
    ....--..............--.........--..............--........--........
    
    "." being '0' and "-" being '1'.
    (Illustration purpose only)

    It should give me a nice pulse signal that is the difference in intervals of the rising edges of sig & sig_reg.

    That means that when sig = '1' at falling_edge(clk), a sig_reg will be produced at the successive rising_edge(clk). However, nothing happens when sig='1' is at the rising_edge(clk), i.e. no pulse signal is produced since sig_reg appears at the same time as sig and difference is zero. So it seems like the code does what it's supposed to do only when the high signal is at the falling_edge(clk).

    Question is: How do I create sexy pulsed signals regardless of whether it is at rising_ or falling_edge(clk)?
    Last edited: Dec 14, 2009
    matchstick86, Dec 14, 2009
    #1
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  2. matchstick86

    matchstick86

    Joined:
    Oct 2, 2009
    Messages:
    19
    It's Halloween in here where ghosts roam...Woooo~~
    matchstick86, Dec 21, 2009
    #2
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