No clock signals found in design

Discussion in 'VHDL' started by Jerry Johns, Aug 27, 2006.

  1. Jerry Johns

    Jerry Johns Guest

    Hello folks,
    I have a top level design for a risc cpu, and i find
    that all though all my pipelined modules run off a single clk signal,
    the top level design during synthesis in Xilinx, does not show timing
    information..it always says, "No clock signals found in design" and "No
    path found" subsequently after..i want to point Xilinx to the fact that
    there is a clk path for which timing info should be displayed so that i
    can later optimize my design accordingly..

    anyone have a clue how to do this? i posted before..but i dont think it
    showed up


    Jerry
     
    Jerry Johns, Aug 27, 2006
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Yttrium
    Replies:
    1
    Views:
    5,668
    David R Brooks
    Nov 27, 2003
  2. Weng Tianxiang

    Signals across two clock domains

    Weng Tianxiang, Dec 17, 2003, in forum: VHDL
    Replies:
    9
    Views:
    5,049
    Mike Treseler
    Dec 22, 2003
  3. GuitarNerd
    Replies:
    8
    Views:
    3,913
    Andy Peters
    May 19, 2005
  4. geoffrey wall

    no clock signals found ... xilinx ise

    geoffrey wall, Jul 27, 2005, in forum: VHDL
    Replies:
    1
    Views:
    3,105
  5. Jerrie85
    Replies:
    2
    Views:
    641
    Jerrie85
    Aug 24, 2006
Loading...

Share This Page