No source after simplification, Xilinx ISE

[golgor]

Hey!
Got a very wierd error when trying to implement this code for a Xilinx - ISE project. It works fine in simluations but when you synthesize you get

Signal p has no source after simplification. This may be due to a non load combinatorial loop.

This makes me confused as i don't even have any signal named p, only a variable.

The purpose of this is to put together a message that will be sent wireless.
4 bits at start to represent the start of the message, 11 bits of data and 1 parity.

I have searched on google and cant find ANYTHING about this.

Much appreciated if anyone know anything about this!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity message is
    Port ( clk : in  STD_LOGIC;
           ce : in  STD_LOGIC;
           ceo : out  STD_LOGIC;
           r : in STD_LOGIC;
           q : out bit);
end message;

architecture behaviour of message is
	signal message : bit_vector (0 to 10) := "01101011100";
	signal startbit : bit_vector (0 to 3) := "0011";
	signal m : bit_vector (0 to 15);
begin
    process(clk, ce, r)
        variable finished : boolean := true;
		  variable i : integer := 0;
		  variable p : bit :='0';
    begin
	     ceo <= '0';
        -- First, put together the message with starting bit sequence and paritybit
      for k in 10 downto 0 loop
			p:=((message(k))xor(p));
		  end loop;
		  m<=startbit & message & p;
        -- Start sending message when CE is enabled
        if (rising_edge(ce)) then
            finished := false;
        end if;
        -- Stop sending message and reset when r is enabled
        if r = '1' then
            finished := true;
            i := 0;
        -- Send bit for bit when we got a clock event (both rising and falling edge)
        elsif ((not finished) and (i/=16)) then
				q<=m(i);
				i:=i+1;
        -- Reset and stop sending when all 16 bits are sent
        else
            finished := true;
            i := 0;
            ceo <= '1';
            q <= '0';
        end if;
    end process;
end behaviour;

 

[joris]

I didn't really look into the code in detail, but the code for the process doesn't really follow the common idioms;
With a clocked process and a reset, use one of these options:

For asynchronous reset:

process(clk,r)
  ...
begin
  if (r = '1') then
    ...
  elsif (rising_edge(clk) then
    ...
  end if;
end process;

For synchronous reset:

process(clk)
  ...
begin
  if (rising_edge(clk) then
    if (r = '1') then
    ...
    else
    ...
    end if;
  end if;
end process;

You have code outside of the rising_edge() check, which seems to "confuse" the synthesis tool.

 

[golgor]

Thanks for answering joris!
Im all new to this, started teaching myself a couple of days ago and only got previous programming skills from common languages. As of now im up to a totalt rewrite to follow the idioms, i hope.

 

[joris]

You probably have a test-bench accompanying this code?

If not, you may first write that, to test the current code (you may find problems you didn't expect, not sure)
Then when reimplementing with the idioms, you are really sure the code is still behaving as expected.

 

[golgor]

You probably have a test-bench accompanying this code?

If not, you may first write that, to test the current code (you may find problems you didn't expect, not sure)
Then when reimplementing with the idioms, you are really sure the code is still behaving as expected.

Im using Xilinx ISE for implementation and ModelSim to simulate everything. Big OK in both programs and wanted behavior in ModelSim should indicate its correct?

Got some minor problems with the new code, i will try to get it right on monday i think. Thanks for the answers Joris.