noob pls help

Discussion in 'VHDL' started by mars12, Jun 24, 2008.

  1. mars12

    mars12

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    hi everybody,
    i want to activate a signal after 12 cycles and then di-activate it again. how can i do that?
    i don't know many things so forgive me if i say anything wrong.
    for example,
    start-0-0-0-0-0-0-0-0-0-0-0-0-1-0-end

    i tried "clock" and "reset" in sensitivity list but in that case "wait" statments weren't accepted.
     
    mars12, Jun 24, 2008
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  2. mars12

    mars12

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    now i wrote this one, but modelsim says,
    error: No feasible emtries for infix operator "+".
    error: Type error resolving infix expression "+" as type ieee.std_logic_1164.std_logic_vector.
    if u have a litle time take a look and help me pls
     
    mars12, Jun 27, 2008
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