Number of TAP nyquist filter

Discussion in 'VHDL' started by Patrick, Jun 11, 2004.

  1. Patrick

    Patrick Guest

    hello,

    I'm working about a DQPSK modem 4 Mbits/s.

    My problem is to implant the 4 nyquist filter (on (I and Q) *2
    (transmitter and receiver).

    I use a Stratix - FPGA.

    When I developp the filter with ONLY 12 taps the four filters utilizes
    76 DSP block and I have only 80 DSP blocks.

    After Matlab simulation, I must have 48 taps for a correct impulse
    response.

    The sampling frequency is 80 MHz and the filter bandpass is 2 MHz.

    Is it possible to implant 4 filters with 48 taps in a single Stratix
    FPGA.

    thanks for response
     
    Patrick, Jun 11, 2004
    #1
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  2. Patrick

    Symon Guest

    Patrick,
    I would suggest you read up about decimation. You can reduce your
    computation requirement considerably, especially as you have a minimum
    theoretical sampling requirement of only 4Msps, i.e. double the bandwidth of
    interest.
    You might also consider using distributed arithmetic. In basic terms, this
    squeezes extra computation out of the FPGA by running it at higher speeds.
    As ever, Google is your mate!
    Cheers, Syms.
    "Patrick" <> wrote in message
    news:...
    > hello,
    > I'm working about a DQPSK modem 4 Mbits/s.
    > My problem is to implant the 4 nyquist filter (on (I and Q) *2
    > (transmitter and receiver).
    > I use a Stratix - FPGA.
    > When I developp the filter with ONLY 12 taps the four filters utilizes
    > 76 DSP block and I have only 80 DSP blocks.
    > After Matlab simulation, I must have 48 taps for a correct impulse
    > response.
    > The sampling frequency is 80 MHz and the filter bandpass is 2 MHz.
    > Is it possible to implant 4 filters with 48 taps in a single Stratix
    > FPGA.
     
    Symon, Jun 11, 2004
    #2
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  3. Patrick

    Ray Andraka Guest

    Yes, but not with the approach you are currently using. You have 80 DSP
    blocks. The multipliers in those are capable of quite a bit more than 80
    MHz. One possibility is to time multiplex the data into the same filter,
    running it at 4x the clock rate. Now 320 MHz is not an easy target,
    especially for a new user. If you are also mixing to baseband, you could
    use a polyphase decimator architecture to reduce the sample rate seen at
    each multiplier. Another option, is to use distributed arithmetic, which
    is a technique whereby the multiplications are rearranged at the bit level
    to take advantage of the small luts in the FPGA fabric. It won't use the
    DSP blocks in that case. As with many things, there is more than one way
    to approach the problem.

    Patrick wrote:

    > hello,
    >
    > I'm working about a DQPSK modem 4 Mbits/s.
    >
    > My problem is to implant the 4 nyquist filter (on (I and Q) *2
    > (transmitter and receiver).
    >
    > I use a Stratix - FPGA.
    >
    > When I developp the filter with ONLY 12 taps the four filters utilizes
    > 76 DSP block and I have only 80 DSP blocks.
    >
    > After Matlab simulation, I must have 48 taps for a correct impulse
    > response.
    >
    > The sampling frequency is 80 MHz and the filter bandpass is 2 MHz.
    >
    > Is it possible to implant 4 filters with 48 taps in a single Stratix
    > FPGA.
    >
    > thanks for response


    --
    --Ray Andraka, P.E.
    President, the Andraka Consulting Group, Inc.
    401/884-7930 Fax 401/884-7950
    email
    http://www.andraka.com

    "They that give up essential liberty to obtain a little
    temporary safety deserve neither liberty nor safety."
    -Benjamin Franklin, 1759
     
    Ray Andraka, Jun 14, 2004
    #3
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