A
Andy Peters
So, what's the point? People still like to use the old Synopsys
libraries and can't be bothered declaring unsigned signals?
libraries and can't be bothered declaring unsigned signals?
It was done because users requested it. So we did it. I helped write
it and I thought it was a bit redundant.
I've never looked at this package. Does it work like the synopsys
library where it provides unsigned arithmetic for the SLV data type?
One of the things I like about the numeric_std library is that I don't
have to type std_logic_vector anymore! I hated that and signed/
unsigned are so much easier on the fingers!
But then I'm currently using Verilog. After a brief trial run I am
finding it is pleasant to work with saving both my fingers and my
brain for the real work I need to get done. I'm not fully conversant
with the language however and may yet find some issues with it that
make me very unhappy. But for now I'm putting aside my VHDL.
Rick
I've never looked at this package. Does it work like the synopsys
library where it provides unsigned arithmetic for the SLV data type?
One of the things I like about the numeric_std library is that I don't
have to type std_logic_vector anymore! I hated that and signed/
unsigned are so much easier on the fingers!
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