numeric_std_unsigned

Discussion in 'VHDL' started by Andy Peters, Jan 31, 2011.

  1. Andy Peters

    Andy Peters Guest

    So, what's the point? People still like to use the old Synopsys
    libraries and can't be bothered declaring unsigned signals?
    Andy Peters, Jan 31, 2011
    #1
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  2. Andy Peters

    rickman Guest

    On Feb 10, 11:19 pm, David Bishop <> wrote:
    > On 1/31/2011 11:16 AM, Andy Peters wrote:
    >
    > > So, what's the point? People still like to use the old Synopsys
    > > libraries and can't be bothered declaring unsigned signals?

    >
    > It was done because users requested it.  So we did it.   I helped write
    > it and I thought it was a bit redundant.


    I've never looked at this package. Does it work like the synopsys
    library where it provides unsigned arithmetic for the SLV data type?

    One of the things I like about the numeric_std library is that I don't
    have to type std_logic_vector anymore! I hated that and signed/
    unsigned are so much easier on the fingers!

    But then I'm currently using Verilog. After a brief trial run I am
    finding it is pleasant to work with saving both my fingers and my
    brain for the real work I need to get done. I'm not fully conversant
    with the language however and may yet find some issues with it that
    make me very unhappy. But for now I'm putting aside my VHDL.

    Rick
    rickman, Feb 11, 2011
    #2
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  3. Andy Peters

    Andy Guest

    On Feb 11, 10:19 am, rickman <> wrote:
    > On Feb 10, 11:19 pm, David Bishop <> wrote:
    >
    > > On 1/31/2011 11:16 AM, Andy Peters wrote:

    >
    > > > So, what's the point? People still like to use the old Synopsys
    > > > libraries and can't be bothered declaring unsigned signals?

    >
    > > It was done because users requested it.  So we did it.   I helped write
    > > it and I thought it was a bit redundant.

    >
    > I've never looked at this package.  Does it work like the synopsys
    > library where it provides unsigned arithmetic for the SLV data type?
    >
    > One of the things I like about the numeric_std library is that I don't
    > have to type std_logic_vector anymore!  I hated that and signed/
    > unsigned are so much easier on the fingers!
    >
    > But then I'm currently using Verilog.  After a brief trial run I am
    > finding it is pleasant to work with saving both my fingers and my
    > brain for the real work I need to get done.  I'm not fully conversant
    > with the language however and may yet find some issues with it that
    > make me very unhappy.  But for now I'm putting aside my VHDL.
    >
    > Rick


    Yes, afaik, it defines arithmetic operators that work on slv, and
    assumes an unsigned binary interpretation of the bits.

    I always create a subtype:

    subtype slv is std_logic_vector;

    Then I can use "slv" anywhere I would use
    "std_logic_vector" (declarations, type conversions, etc.)

    I'm betting that if you ever do much fixed point arithmetic, you'll be
    back. But it's a good thing to know more than one HDL language.

    Andy
    Andy, Feb 11, 2011
    #3
  4. Andy Peters

    JimLewis Guest


    > > > So, what's the point? People still like to use the old Synopsys
    > > > libraries and can't be bothered declaring unsigned signals?

    >
    > > It was done because users requested it.  So we did it.   I helped write
    > > it and I thought it was a bit redundant.

    >
    > I've never looked at this package.  Does it work like the synopsys
    > library where it provides unsigned arithmetic for the SLV data type?
    >
    > One of the things I like about the numeric_std library is that I don't
    > have to type std_logic_vector anymore!  I hated that and signed/
    > unsigned are so much easier on the fingers!


    I think using the types unsigned and signed everywhere instead of SLV
    is a good idea. In fact, if you don't use numeric_std_unsigned and
    you use std_logic_vector with a relational operator, life is bad.
    OTOH, if you are careful, you never need numeric_std_unsigned for
    RTL.

    The one place I like numeric_std_unsigned though is in testbenches.
    When an address input to a DUT is std_logic_vector and I want to
    algorithmically add one to it, I find the code much more readable
    if I use numeric_std_unsigned than use one of the numerous different
    approaches that use type conversions. When you consider readability,
    you need to consider not just people who are at your skill level, but
    also the people who will take on maintaining the design.

    As Andy mentioned, mentioned, what is the point, people still use the
    old std_logic_arith and std_logic_unsigned. My answer to that is it
    is hard to get people to transition if you don't give them the
    packages they want to use when they transition - namely
    numeric_std_unsigned
    was missing. So hopefully we can get them to transition.

    Going further, it would be nice if vendor documentation, notably
    Xilinx (at least through 12.1) replacing std_logic_arith with
    numeric_std.

    Best,
    Jim
    JimLewis, Feb 15, 2011
    #4
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