[O.T] SystemC benefits?

Discussion in 'VHDL' started by Jezwold, Feb 7, 2005.

  1. Jezwold

    Jezwold Guest

    I know its off topic but I couldn't find a systemc forum.
    What are the benefits for an engineer who uses vhdl and knows how to
    program in C in moving to SystemC for simulation/synthesis?I get the
    impression that systemc is very much a behavioural modelling system are
    the synthesis tools better at behavioural synthesis than the current
    vhdl tool sets? Is it suitable for use in all situations where vhdl can
    be used or are there situations where one is better suited than the
    other.Is the industry moving towards behavioural synthesis in general?
    Most of the examples I have seen leave a lot to be desired.
     
    Jezwold, Feb 7, 2005
    #1
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  2. Jezwold

    Neo Guest

    I think systemC isn't actually intended for synthesis eventhough
    constructs have been added for that prupose. its main purpose is in
    raising the level of abstraction which helps in system modelling with
    both hardware and software represented and verification at transaction
    levels. I dont think anybody's using commercial tools offering
    systhesis from systemc though some systhesizers are around which do
    that from handleC and systemC.
    Its not a replacement for VHDL or verilog, which will continue to be
    used for describing RTL.
     
    Neo, Feb 8, 2005
    #2
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  3. Jezwold

    Jezwold Guest

    Thanks,its just that i had some guy wanting to sell me handelC which is
    plain old C rather than C++ as systemC is but it claims to do the same
    sort of things and I was just wondering how useful it might be.I think
    some of the claims he was making for it were a little optimistic to say
    the least
     
    Jezwold, Feb 8, 2005
    #3
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