odd and even signals

Discussion in 'VHDL' started by Patrick, Dec 21, 2004.

  1. Patrick

    Patrick Guest

    hello

    I would like to know how to produce the bit signal with 2 baud signals
    for DQPSK demodulation
    I is the odd of the bit signal and Q is the even signal of bit signal

    clk_bit is twice clk_baud

    I have two signals I and Q and I want to generate out_bit with these
    two signals I and Q

    I made it like this but I think that it is not the right solution

    Do you have suggestion about this design ?

    signal I, Q : in std_logic;

    ECH_IQ : process (init,clk_baud)
    begin
    if init='1' then
    I_i <= '0';
    Q_i <= '0';
    elsif (clk_baud'event and clk_baud='1') then
    I_i <= I;
    Q_i <= Q;
    end if;
    end process ECH_IQ;

    C1 <= I_i AND clk_baud; -- here i put the odd signal into C1
    D1 <= Q_i AND (NOT clk_baud); -- and here the event signal into D1

    -- I think it's not good to do a logic operator between a clock and a
    signal

    SIG_OUT_BIT : process (init,clk_bit)
    begin
    if init='1' then
    out_bit <= '0';
    elsif (clk_bit'event and clk_bit='1') then
    out_bit <= D1 OR C1;
    end if;
    end process SIG_OUT_BIT;
    Patrick, Dec 21, 2004
    #1
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  2. On 21 Dec 2004 06:41:49 -0800, (Patrick)
    wrote:

    [description of something that is essentially a
    Double Data Rate receiver]

    >clk_bit is twice clk_baud


    How are these two clocks related? It matters very much.

    >-- I think it's not good to do a logic operator
    > between a clock and a signal


    I think I agree, rather strongly - if the signal is
    synchronous to that same clock.

    The code you describe is a rather long-winded way to
    describe a multiplexer; it's much easier to describe
    like this:

    process (init, clk_bit)
    begin
    if init = '1' then
    out_bit <= '0';
    elsif rising_edge (clk_bit) then
    if clk_baud = '1' then
    out_bit <= I_i;
    else
    out_bit <= Q_i;
    end if;
    end if;
    end process;

    However, this is not necessarily correct. It depends
    on the timing relationship between clk_bit and clk_baud.
    It may be that you know this, because (perhaps) you
    derived clk_baud by dividing clk_bit by 2, or some
    similar idea. If you *don't* know the relationship,
    things get a great deal more difficult. Indeed, this is
    the root of your concern about gating a clock with other
    signals (which my code also does, albeit in a less
    obvious way).
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Dec 21, 2004
    #2
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