Odd Oversampling

Discussion in 'VHDL' started by ALuPin, Apr 18, 2005.

  1. ALuPin

    ALuPin Guest

    Hi newsgroup,

    maybe someone of you out there has faced some similar problem:

    I want to sample 16MHz data with a 125MHz clock.

    But 125/16 = 7.8125

    Is there some tricky method to perform this kind of oversampling ?

    The only thing I know is the Bresenham algorithm, but could that
    be the solution ?

    Thank you in advance.

    Rgds
     
    ALuPin, Apr 18, 2005
    #1
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  2. ALuPin wrote:

    > I want to sample 16MHz data with a 125MHz clock.
    > Is there some tricky method to perform this kind of oversampling ?


    There's a simple one if you have both clocks.
    Write a synchronous process using 125MHz
    as the clock and 16MHz as an input named "rate"
    Synchronize "rate" and use it to generate a
    rate_rising clock enable pulse.

    -- Mike Treseler
     
    Mike Treseler, Apr 18, 2005
    #2
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  3. ALuPin

    ALuPin Guest

    "Symon" <> wrote in message news:<>...
    > "Jonathan Bromley" <> wrote in message
    > news:...
    > > If you don't have access to the original 16MHz clock, you can
    > > either try to recover it by locking a digital PLL on to the
    > > data transitions (7x oversampling is *just* about enough
    > > to be able to do this easily)

    >
    > It's easy enough with just 4 times oversampling. XAPP224 shows how to do it
    > at 400Mb+ data rates.
    > Cheers, Syms.

    Please correct me if I got the problem wrong.

    Is it right that I could define a counter (clocked with 125MHz)
    and define one counter position as the sample point which is located
    in the middle position neighborhood of the bit to sample ?
    The counter would be quasi started if the first transition is
    recognized. This transition could be recognized with a two stage flip
    flop chain in the 125Mhz
    clock domain.
    The problem would be that the following sample points would walk
    because
    125/16 is a fraction number. Is that right ?

    Could that sample point walk even then if the oversample factor 125/x
    would
    be an integer number for example 120MHz/12MHz when 120MHz having 0.05%
    tolerance
    and 20MHz having 0.02% tolerance ?


    If I have 7 times oversampling would I need then an input stage
    with seven stages (XAPP224)? What additional clocks would I need then
    ?
    Or are four clocks sufficient?

    Thank you in advance.

    Rgds
    André
     
    ALuPin, Apr 19, 2005
    #3
  4. ALuPin

    ALuPin Guest

    One more question:

    The quasi "oversample" solution in XAPP224 does imply that the sample
    clock is the same as the clock from the incoming data stream.

    But in my situation I have a clock that is 7-8 times faster.

    Please clarify ...

    Thank you.

    Rgds
    André
     
    ALuPin, Apr 19, 2005
    #4
  5. ALuPin

    Symon Guest

    Hi André,
    I'd probably do it like this.
    Have a 7 bit counter that counts modulo 125 on your 125MHz clock. Call it
    'counter'. If you get a transition on the data (which you've already sampled
    into the 125MHz clock domain, right?), reset it to 0. When the counter says
    4 | 12 | 19 | 27 | 35 | 43 | 51 | 58 | 66 | 74| 82 | 90 | 97 | 105 | 113 |
    121 sample the data. (I'd check those numbers for yourself, my arithmetic
    isn't what it used to be..) Of course with half the bits there will be a
    transition so you'll only be sampling at big counts if you get a lot of
    consecutive equal bits. Remember if the count gets to 124 the next count
    should be 0, i.e. modulo 125.
    Have fun, Syms.

    "ALuPin" <> wrote in message
    news:...
    > Hi newsgroup,
    >
    > maybe someone of you out there has faced some similar problem:
    >
    > I want to sample 16MHz data with a 125MHz clock.
    >
    > But 125/16 = 7.8125
    >
    > Is there some tricky method to perform this kind of oversampling ?
    >
    > The only thing I know is the Bresenham algorithm, but could that
    > be the solution ?
    >
    > Thank you in advance.
    >
    > Rgds
     
    Symon, Apr 19, 2005
    #5
  6. ALuPin

    Peter Alfke Guest

    Here is a circuit that generates 16 MHz from a 125 MHz clock:
    Use a Xilinx DCM with simultaneous multiply by 16 and division by 25.
    That gives you 80 MHz, which might be convenient for 5x oversampling.
    Peter Alfke, Xilinx Applications
     
    Peter Alfke, Apr 19, 2005
    #6
  7. ALuPin

    Symon Guest

    Personally I probably wouldn't do this, depending on the situation. I find
    that having as few clocks as possible is the best strategy for FPGAs. I use
    enables instead. So, if Andre already has a 125MHz system clock in his
    device that he's using, he should stick with it rather than generating a new
    clock domain. If, however, the 125MHz is only used in this circuit, I guess
    making it into 80MHz might work.
    YMMV, Syms.
    p.s. I think all my numbers in that previous post were 1 too big for a
    proper sync design.
    "Peter Alfke" <> wrote in message
    news:...
    > Here is a circuit that generates 16 MHz from a 125 MHz clock:
    > Use a Xilinx DCM with simultaneous multiply by 16 and division by 25.
    > That gives you 80 MHz, which might be convenient for 5x oversampling.
    > Peter Alfke, Xilinx Applications
    >
     
    Symon, Apr 19, 2005
    #7
  8. ALuPin wrote:

    > But in my situation I have a clock that is 7-8 times faster.
    > Please clarify ...


    Please reread my posting.
    The idea is as clear as I have time to make it.

    -- Mike Treseler
     
    Mike Treseler, Apr 19, 2005
    #8
  9. ALuPin

    Symon Guest

    I just reread your post. Where does the 16 MHz clock come from? Rereading
    Andre's original post, he only has 16 MHz (sic) data. ;-)
    Cheers, Syms.
    "Mike Treseler" <> wrote in message
    news:...
    > ALuPin wrote:
    >
    > > But in my situation I have a clock that is 7-8 times faster.
    > > Please clarify ...

    >
    > Please reread my posting.
    > The idea is as clear as I have time to make it.
    >
    > -- Mike Treseler
     
    Symon, Apr 19, 2005
    #9
  10. ALuPin

    ALuPin Guest

    The 16MHz stands for an external data stream. I have no direct clock
    recovery of that data stream. The 125MHz comes from a PLL. The input
    clock of the PLL
    is not the source clock of the data stream.

    I will think about your suggestions.

    Thank you to all.

    Rgds
    André
     
    ALuPin, Apr 20, 2005
    #10
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