Ok, so now what?

[usao]

Ok, so I just recently found out about VHDL. Im interested in
simulating a digital circuit to see how it works. I built a simple
VHDL script, but now I don't see any way to run this script. Im on Sun
Solaris 9, and aparently, you need a seperate compiler other than GCC
to compile this.
Is VHDL compiled to binary then run or is it more of an interpreted
(shell-like) language where you run under an interpreter? Does anyone
know where I can find either a compiler or an interpreter for this?
Anti-spam email: rwatkins at dssolutions dot com.

 

[Ralf Hildebrandt]

usao wrote:

Ok, so I just recently found out about VHDL. Im interested in
simulating a digital circuit to see how it works. I built a simple
VHDL script, but now I don't see any way to run this script. Im on Sun
Solaris 9, and aparently, you need a seperate compiler other than GCC
to compile this.

VHDL is not connected to any operating system. GCC is a software
compiler. VHDL is a hardware description language.

Is VHDL compiled to binary then run or is it more of an interpreted
(shell-like) language where you run under an interpreter?

No, you need a simulator-environment (consisting of a compiler,
elaborator and simulator).

Does anyone
know where I can find either a compiler or an interpreter for this?

Do not program VHDL. A HDL is a hardware description languaga. You have
to model hardware. Don't think in C-style.


Ralf

 

[Jim Wu]

Take a look at comp.lang.vhdl FAQ at http://www.vhdl.org/vi/comp.lang.vhdl/

Jim Wu
(e-mail address removed) (remove capital letters)
http://www.geocities.com/jimwu88/chips

 

[Mike Treseler]

Ok, so I just recently found out about VHDL. Im interested in
simulating a digital circuit to see how it works. I built a simple
VHDL script, but now I don't see any way to run this script.

You need a simulator like Modelsim.

vlib work
vmap work work
vcom my_script.vhd
vsim -c my_script -do "run"


related thread
http://groups.google.com/groups?q=simulator+environment+Ramenan


-- Mike Treseler

 

[John Williams]

You need a simulator like Modelsim.

vlib work
vmap work work
vcom my_script.vhd
vsim -c my_script -do "run"

While the other comments about modeling vs compiling are true, and
essential in the "mind set" for VHDL, I should mention GHDL, which is a
gcc extension to compile VHDL into a simulation model.

http://ghdl.free.fr/

Regards,

John