N
Nikos Kostis
Hi,
I'm doing an MSc project that involves an AMBA-based architecture. The
current AMBA spec (v2.0, IHI 0011a) only provides timing diagrams of
the bus functionality. It is indeed possible to create HDL state
machines out of these, but I've read in older posts that these state
machines were provided in older versions of the spec. Does anybody
know where I can get hold of these documents or anything relevant?
(www.arm.com does not seem to help)
Moreover I am trying to find documentation on AHB master and slave
wrappers. Some old postings again refer to an ARM guide on wrappers
(DDI 0169b) which is again nowhere to be found in the ARM website. Is
there some archive of older documentation, or can someone point to any
good source of documentation on wrappers?
Finally, in order to create a core that is both an AHB master and
slave (a DMA controller in particular), I suppose that i have to code
both master and slave interfaces in the top-level of the core, making
most (if not all) control signals of type inout, and correctly
separating inputs and outputs inside the core.
Is there a more efficient solution? (I would suppose that this issue
is quite trivial).
Thanks for any responses
Nikos Kostis
(Institute for System Level Integration, Scotland, UK)
I'm doing an MSc project that involves an AMBA-based architecture. The
current AMBA spec (v2.0, IHI 0011a) only provides timing diagrams of
the bus functionality. It is indeed possible to create HDL state
machines out of these, but I've read in older posts that these state
machines were provided in older versions of the spec. Does anybody
know where I can get hold of these documents or anything relevant?
(www.arm.com does not seem to help)
Moreover I am trying to find documentation on AHB master and slave
wrappers. Some old postings again refer to an ARM guide on wrappers
(DDI 0169b) which is again nowhere to be found in the ARM website. Is
there some archive of older documentation, or can someone point to any
good source of documentation on wrappers?
Finally, in order to create a core that is both an AHB master and
slave (a DMA controller in particular), I suppose that i have to code
both master and slave interfaces in the top-level of the core, making
most (if not all) control signals of type inout, and correctly
separating inputs and outputs inside the core.
Is there a more efficient solution? (I would suppose that this issue
is quite trivial).
Thanks for any responses
Nikos Kostis
(Institute for System Level Integration, Scotland, UK)