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Hi all !
I need to write a VHDL program to test the data and address lines of DDR interface with Virtex FPGA. The idea is to write a routine in FPGA which automatically scans the DDR interface, on power on, for any error in Address and Data lines. The program should be able to identify the exact problem area and stores the same in a register within the FPGA.
I would really appreciate any pointer or approach to handle this problem.
thanks and regards,
I need to write a VHDL program to test the data and address lines of DDR interface with Virtex FPGA. The idea is to write a routine in FPGA which automatically scans the DDR interface, on power on, for any error in Address and Data lines. The program should be able to identify the exact problem area and stores the same in a register within the FPGA.
I would really appreciate any pointer or approach to handle this problem.
thanks and regards,