onboard DDR testing !

Joined
Nov 21, 2006
Messages
31
Reaction score
0
Hi all !

I need to write a VHDL program to test the data and address lines of DDR interface with Virtex FPGA. The idea is to write a routine in FPGA which automatically scans the DDR interface, on power on, for any error in Address and Data lines. The program should be able to identify the exact problem area and stores the same in a register within the FPGA.

I would really appreciate any pointer or approach to handle this problem.

thanks and regards,
 
Joined
May 4, 2007
Messages
49
Reaction score
0
Remember to wait after power up for the DDR initialization time to complete. Then create a single up-counter (0 to 2^x) that connects to the address and data lines. If data is 32 bits and address is say 12 bits then assign those 12 bits to the data lines multiple times. So do a full write first. Then when you do a read run the same up-counter and compare the DDR memory data output against an internal counter. Any errors should be shoved into a fifo for reading out of a register upon completion.

A more thourough test would be to include a walking 1's pattern, 0xAAAA's and 0x5555's as well.

Then you should switch to Altera because all these tests come standard when you use the DDR memory interface built into the Core.

Regards,
Scott (Altera all the way)
 
Joined
Nov 21, 2006
Messages
31
Reaction score
0
Thanks Scottcarl, if I understand you correctly, I need to feed data lines with a defined pattern (say AAAA or 5555) and the counter will generate the required addresses for write operation, then the same counter would be used for read operation. Then there will be an internal comparator which will compare the write and read values corresponding to each counter increment. Any error in comparision would be reported as a fault in data lines.

But this takes care of Data lines. What about Address lines testing ? Perhaps I have not understood you completly !

My interface has 13 bit address lines and 64 bit data interface.
 
Joined
May 4, 2007
Messages
49
Reaction score
0
Try this:

addr <= addr + '1'; -- start at 0 and run to (2^13)-1

Test 1: Counting pattern
ddr_addr <= addr;
ddr_data <= addr(11 downto 0) & addr & addr & addr & addr;

Test 2: Walking 1's
ddr_addr <= addr;
ddr_data(64 downto 1) <= ddr_data(63 downto 0); -- ddr_data(0)=1
(pattern ..00001 00002 00004 00008 00010 00020 etc...)

Test 3: A's and 5's
ddr_addr <= addr
ddr_data <= X"AAAA ..."; alternate with X"5555 ...";

After writing a Test, then read back using the same addr and comparing against the expected data and store any failures into a FIFO.

Scott
 
Joined
Nov 21, 2006
Messages
31
Reaction score
0
Thanks Scottcarl, this was indeed a valuable input from you. Well, I think fault with addresses lines or data lines can be deduced from the fact that, if Data line is corrupt, then it will show error with every read and write operation. On the other hand if there is a problem in address line than only a specific location will show error. Am I right in this interpretation ?

:einstein:
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

No members online now.

Forum statistics

Threads
473,743
Messages
2,569,478
Members
44,899
Latest member
RodneyMcAu

Latest Threads

Top