One-element constant array

A

Amal

How does one declare an array constant with only one element?

type a_t is array(natural range <>) of std_logic_vector(7 downto 0);

constant a1 : a_t := (
"00000000"
);
constant a2 : a_t := (
"00000000",
"00000001"
);

a2 passes compiler, but a1 gives error:

###### test.vhd(26): "00000000"
#
# ** Error: test.vhd(26): String literal found where type a_t, whose
element type ieee.std_logic_1164.std_logic_vector is not an
enumeration type, was expected.


The following works, but is there any other ways?

constant a1 : a_t := (
0=> "00000000"
);

-- Amal
 
J

Jonathan Bromley

How does one declare an array constant with only one element?

type a_t is array(natural range <>) of std_logic_vector(7 downto 0);

constant a1 : a_t := (
"00000000"
);
constant a2 : a_t := (
"00000000",
"00000001"
);

a2 passes compiler, but a1 gives error:

###### test.vhd(26): "00000000"
#
# ** Error: test.vhd(26): String literal found where type a_t, whose
element type ieee.std_logic_1164.std_logic_vector is not an
enumeration type, was expected.


The following works, but is there any other ways?

constant a1 : a_t := (
0=> "00000000"
);

I think the problem is that if your aggregate contains only
one element, the compiler thinks its parentheses are just
ordinary parens around an expression and can't work out
that they're enclosing an aggregate.

I agree it's tedious, but the named association
0=>...
is hardly a big problem.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
C

Colin Paul Gloster

On Fri, 19 Oct 2007, Jonathan Bromley wrote:

|-----------------------------------------------------------------------|
| |
|>How does one declare an array constant with only one element? |
|> |
|> type a_t is array(natural range <>) of std_logic_vector(7 downto 0);|
|> |
|> constant a1 : a_t := ( |
|> "00000000" |
|> ); |
|> constant a2 : a_t := ( |
|> "00000000", |
|> "00000001" |
|> ); |
|> |
|>a2 passes compiler, but a1 gives error: |
|> |
|> ###### test.vhd(26): "00000000" |
|> # |
|> # ** Error: test.vhd(26): String literal found where type a_t, whose|
|>element type ieee.std_logic_1164.std_logic_vector is not an |
|>enumeration type, was expected. |
|> |
|> |
|>The following works, but is there any other ways? |
|> |
|> constant a1 : a_t := ( |
|> 0=> "00000000" |
|> ); |
|" |
|-----------------------------------------------------------------------|

No other way exists. See
4.2.4 Aggregates/Arrays Containing a Single Element
on
WWW.VHDL.org/comp.lang.vhdl/FAQ1.html#aggregates

N.B. This has nothing to do with the reserved word constant.

|-----------------------------------------------------------------------|
|"I think the problem is that if your aggregate contains only |
|one element, the compiler thinks its parentheses are just |
|ordinary parens around an expression and can't work out |
|that they're enclosing an aggregate. |
| |
|I agree it's tedious, but the named association |
| 0=>... |
|is hardly a big problem." |
|-----------------------------------------------------------------------|

That is one way of expressing it.

Regards,
Colin Paul Gloster
 

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