One Hot FSM stuck !!

Discussion in 'VHDL' started by Nic, Feb 26, 2004.

  1. Nic

    Nic Guest

    Hi

    I have a desgn that has a one hot FSM.
    I'm using ISE Webpack 6.1 and XST to synth the VHDL.
    Somtimes the design locks up, using Chipscope, I've been able to probe
    the state of the FSM machine and it's locked up with no states active.

    This is impossible I know.

    Does anyone have any idea on how this could happen ?
    This problem is driving us mad.

    Thanks

    Nic
    Nic, Feb 26, 2004
    #1
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  2. Nic wrote:


    > Somtimes the design locks up, using Chipscope, I've been able to probe
    > the state of the FSM machine and it's locked up with no states active.


    Maybe a hazard on an asynchronous reset?
    Maybe a hazard on a signal, that chooses which state is next short
    before the clock-edge?

    Ralf
    Ralf Hildebrandt, Feb 26, 2004
    #2
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  3. Nic wrote:
    > Hi
    >
    > I have a desgn that has a one hot FSM.
    > I'm using ISE Webpack 6.1 and XST to synth the VHDL.
    > Somtimes the design locks up, using Chipscope, I've been able to probe
    > the state of the FSM machine and it's locked up with no states active.
    >
    > This is impossible I know.
    >
    > Does anyone have any idea on how this could happen ?
    > This problem is driving us mad.
    >
    > Thanks
    >
    > Nic


    Hi,

    The only way to have the trouble are :

    - asyncronous circuit
    - frequency system too high for you circuit.

    First, makesure to synchronize all input of your FSM.
    Second, goto to the P&R static timing report of your design and check
    the max frequency corresponding with the most significant pass in your
    logic level.

    Regards,
    Laurent
    www.amontec.com

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    Amontec Team, Laurent Gauch, Feb 26, 2004
    #3
  4. Nic wrote:

    > I have a desgn that has a one hot FSM.
    > I'm using ISE Webpack 6.1 and XST to synth the VHDL.
    > Somtimes the design locks up, using Chipscope, I've been able to probe
    > the state of the FSM machine and it's locked up with no states active.
    >
    > This is impossible I know.
    >
    > Does anyone have any idea on how this could happen ?
    > This problem is driving us mad.


    Consider binary encoding.

    http://groups.google.com/groups?q=one-hot log2 utilization

    -- Mike Treseler
    Mike Treseler, Feb 27, 2004
    #4
  5. Nic <> wrote in message news:<>...
    > Hi
    >
    > I have a desgn that has a one hot FSM.
    > I'm using ISE Webpack 6.1 and XST to synth the VHDL.
    > Somtimes the design locks up, using Chipscope, I've been able to probe
    > the state of the FSM machine and it's locked up with no states active.
    >
    > This is impossible I know.
    >
    > Does anyone have any idea on how this could happen ?
    > This problem is driving us mad.
    >


    I had a similar problem. My FSM was sometimes stuck when a cable was
    removed or inserted while the board was powered. All inputs to the FSM
    where synchronised with dual flip-flops. Then solution was to put an
    attribute in the VHDL code to get binary coding of the FSM. To cover
    all unused states in the FSM is also good design practice.

    /Peter
    Peter Hermansson, Feb 27, 2004
    #5
  6. Nic

    FGreen Guest

    (Peter Hermansson) wrote in message news:<>...
    > Nic <> wrote in message news:<>...
    > > Hi
    > >
    > > I have a desgn that has a one hot FSM.
    > > I'm using ISE Webpack 6.1 and XST to synth the VHDL.
    > > Somtimes the design locks up, using Chipscope, I've been able to probe
    > > the state of the FSM machine and it's locked up with no states active.
    > >
    > > This is impossible I know.
    > >
    > > Does anyone have any idea on how this could happen ?
    > > This problem is driving us mad.
    > >

    >
    > I had a similar problem. My FSM was sometimes stuck when a cable was
    > removed or inserted while the board was powered. All inputs to the FSM
    > where synchronised with dual flip-flops. Then solution was to put an
    > attribute in the VHDL code to get binary coding of the FSM. To cover
    > all unused states in the FSM is also good design practice.
    >
    > /Peter


    Are you using async. reset? That is suspicion, as someone suggested
    earlier. If this async. reset isn't taken care of properly, it can
    cause exactly what the orig. poster described. Making the state var.
    binary would solve the problem, but that doesn't cure the underlying
    issue. Using GSR of startup block would exacerbate the problem, by
    the way.

    I used to code with async. reset, and now I'm a big proponent of sync.
    reset. It requires more work, but pays off.
    FGreen, Mar 2, 2004
    #6
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