One simple quesiton

[parag_paul]

This might be very simple , sorry for wasting your time.

I have seen terms like level sensitive and edge sensitive..

Now hoe can anythign be level sensitive, the value has to change at
the edge no matter what,
I want to understand , that latches are said to be level senstitive,
now, the x output of SR latch ( for example) Will become s or r from
0,0 input state only when one of them changes to 1 right, How can we
call it a level sensitive device.

Thanks in advance again

 

[MikeShepherd564]

Concerning latches, "edge-sensitive" indicates that the latch contents
may change only at a clock transition; "level-sensitive" suggests
that the contents may change while the "enable" signal is in its
"active" state (transparent latch).

The terms "edge-triggered" and "level-triggered" are also used.

Don't seek any deep meaning or accuracy in these terms. They are used
(like most words) without much thought. You may see them in data
sheets, but you should read the detailed description in order properly
to understand the function.

 

[Ole Nielsby]

I have seen terms like level sensitive and edge sensitive..

Me thinks parachutes are level sensitive and airbags are edge
sensitive. Your parachute will (hopefully) automatically unfold
when the air pressure reaches a certain level. Your airbag will
explode at a sudden move.

If you want a better explanation, you should incorporate the
terms you want explained in the subject line. Call it:

Level/edge sensitive - could someone explain?

or something like that. That's more likely to catch the eyes of
the experts.

 

[Duane Clark]

This might be very simple , sorry for wasting your time.

I have seen terms like level sensitive and edge sensitive..

Now how can anythign be level sensitive, the value has to change at
the edge no matter what,
I want to understand , that latches are said to be level senstitive,
now, the x output of SR latch ( for example) Will become s or r from
0,0 input state only when one of them changes to 1 right, How can we
call it a level sensitive device.

level_sensitive: process (A, EN)
begin
if EN = '1' then
B <= A;
end if;
end process level_sensitive;

Notice that there is no clock involved. There are real situations where
you might want that behavior, though almost never in an FPGA. That is
why the synthesis tools warn you if you have inadvertently created a latch.

In the (very) old days of building microprocessor memory interfaces with
TTL logic, they were used rather commonly. These are commonly referred
to as transparent latches, because when the enable is active, the device
is transparent. For example, google for the 74LS75 device. Notice that
there is no clock pin on the device.