Open Drain

[tancming]

Hi

I am new to VHDL. I am trying to implement I2C slave and have problem ACKing the 9th bit in the SDA line.

Basically I have a Master sending the Slave address and as a Slave on the CPLD, i tried to do ACK on the SDA line but I only get a glitch instead of a low for ACK. Can you please help?

I have a bit counter that count the incoming bits of the SCL. For every falling edge on the SCL, the BitCounter counts by one. On the falling edge of the 8th clock, the BitCounter = 9.

Then when I detect the rising edge of the next SCL (9th), I tried to pull the SDA low but I only get a glitch.

Here is my code,

SDen <= '1' when ((BitCounter = 9) and (SCL_int='1')) else '0';

SDen is the signal I used to change the SDA line from 'Z' to a output Low. It is connected to the upper level and is connected to OE.
SDen => OE

On the top level, I have OE change SDA to output low. SDA is declared as an inout pin.
SDA <= '0' when OE = '1' else 'Z';

Can you please help?

Thanks
VHDL new

 

[tancming]

If I changed the code to the below, then it works. Basically i just removed the SCL_int='1'. However by removing that I pulled the aCK bit low not at the time when SCL is low but even before it, i.e. the ACK bit is pulled low as soon as Bitcounter=9, meaning at the time the 8th clock's falling edge to the 9th clock's falling edge. Although it works, it violates the I2C timing spec.

changed from
SDen <= '1' when ((BitCounter = 9) and (SCL_int='1')) else '0';
to this and it works
SDen <= '1' when ( BitCounter = 9 ) else '0';

(Note: BitCounter counts to 9 at SCL 8th Bit's falling edge)

Please help, why can't I pulled the SDA low at the time between SCL_int is rising and falling during the 9th bit?