open inputs and Unisim libraries

Discussion in 'VHDL' started by Brian Davis, Jun 15, 2006.

  1. Brian Davis

    Brian Davis Guest

    Has anyone else seen problems with changes to the
    latest Xilinx 8.1 Unisim libraries?

    I loaded up 8.1sp3 to do some S3E test code; structural code
    that worked fine with 6.x now chokes XST because the newer
    Unisim library lacks the default values needed to use 'open' on
    unused primitive inputs. ( e.g. BUFGMUX with only I1 in use )

    Replacing all the "open"s with '0' works at the expense of a routed
    '0' net running around the chip.

    Short of manually editing the Unisim library, or declaring all the
    primitives myself, anyone know of another workaround?

    Brian

    6.3 unisim_vcomp.vhd BUFGMUX declaration:

    component BUFGMUX
    port
    (
    O : out std_ulogic := '0';
    I0 : in std_ulogic := '0';
    I1 : in std_ulogic := '0';
    S : in std_ulogic := '0'
    );
    end component;

    8.1 unisim_vcomp.vhd BUFGMUX declaration:

    component BUFGMUX
    port
    (
    O : out std_ulogic;
    I0 : in std_ulogic;
    I1 : in std_ulogic;
    S : in std_ulogic
    );
    end component;
     
    Brian Davis, Jun 15, 2006
    #1
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