Open Source VHDL Verification Methodology

[HT-Lab]

For those that haven't seen it,

http://www.aldec.com/en/solutions/functional_verification/os_vvm

Hans
www.ht-lab.com

 

[hssig]

Hi,

I have tried the fifo example with Modelsim, the simulation performs
as expected.
In my opinion the adoption of coverage definition and collection
seems not that easy because there are some complex dependencies.
Nevertheless I will give a try in my next own testbench.

Cheers, hssig

 

[JimLewis]

Also don't miss that there will be a webinar on Thursday Jan 26.
Go to: http://www.aldec.com/en/events

The presentation examples will be similar to the examples
in the user guides for the individual packages. Currently
the user guides are only available at:
http://www.synthworks.com/downloads

@hssig

In my opinion the adoption of coverage definition and
collection seems not that easy because there are some
complex dependencies.

With OS-VVM/CoveragePkg, coverage can be modeled
incrementally, and hence, you can create as complicated
coverage model as you are willing to write.

If you find a problem that you don't think it can
handle, drop me a line. I have numerous revision
plans for the package, maybe we will learn that some
are more important than others.

Best Regards,
Jim
SynthWorks VHDL Training

 

[hssig]

Currently the user guides are only available at: http://www.synthworks.com/downloads

Thank you for the link.

Cheers, hssig

 

[HT-Lab]

Thank you for the link.

Cheers, hssig

Just found:

http://testosvvm.webs.com/

www.osvvm.org is still redirected to Aldec but it looks like there is
some effort going on to make it EDA vendor neutral (which we obviously
something we want).

Regards,
Hans.
www.ht-lab.com