Open Source VHDL Verification Methodology

Discussion in 'VHDL' started by HT-Lab, Jan 20, 2012.

  1. HT-Lab

    HT-Lab Guest

    HT-Lab, Jan 20, 2012
    #1
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  2. HT-Lab

    hssig Guest

    Hi,

    I have tried the fifo example with Modelsim, the simulation performs
    as expected.
    In my opinion the adoption of coverage definition and collection
    seems not that easy because there are some complex dependencies.
    Nevertheless I will give a try in my next own testbench.

    Cheers, hssig
     
    hssig, Jan 24, 2012
    #2
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  3. HT-Lab

    JimLewis Guest

    Also don't miss that there will be a webinar on Thursday Jan 26.
    Go to: http://www.aldec.com/en/events

    The presentation examples will be similar to the examples
    in the user guides for the individual packages. Currently
    the user guides are only available at:
    http://www.synthworks.com/downloads

    @hssig
    > In my opinion the adoption of coverage definition and
    > collection seems not that easy because there are some
    > complex dependencies.

    With OS-VVM/CoveragePkg, coverage can be modeled
    incrementally, and hence, you can create as complicated
    coverage model as you are willing to write.

    If you find a problem that you don't think it can
    handle, drop me a line. I have numerous revision
    plans for the package, maybe we will learn that some
    are more important than others.

    Best Regards,
    Jim
    SynthWorks VHDL Training
     
    JimLewis, Jan 25, 2012
    #3
  4. HT-Lab

    hssig Guest

    hssig, Jan 30, 2012
    #4
  5. HT-Lab

    HT-Lab Guest

    HT-Lab, Feb 27, 2012
    #5
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