operation in procdure

Discussion in 'VHDL' started by IcYdRIP, Apr 13, 2005.

  1. IcYdRIP

    IcYdRIP Guest

    I have to reuse the same call many times. so I plan to use a procedure.
    I've read the reference manual and some books, But I still don't know
    if it's possible to use a clock signal from entity in the procedure. I
    mean, if there's a clk signal in the entity, and I define a procedure
    in the package, the declaration as follow for example:

    procedure dm9000_rd_data(signal clk : in std_logic; reg : in
    std_logic_vector(7 downto 0); signal daBus : inout std_logic_vector(7
    downto 0); signal cmd, cs, iowait, rd : out std_logic;);

    and can I use the clk as it's in a entity? such as clk's events and
    values. or I can just read the clk value only?

    thanks!
     
    IcYdRIP, Apr 13, 2005
    #1
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  2. IcYdRIP wrote:
    > I have to reuse the same call many times. so I plan to use a procedure.
    > I've read the reference manual and some books, But I still don't know
    > if it's possible to use a clock signal from entity in the procedure. I
    > mean, if there's a clk signal in the entity, and I define a procedure
    > in the package, the declaration as follow for example:
    >
    > procedure dm9000_rd_data(signal clk : in std_logic; reg : in
    > std_logic_vector(7 downto 0); signal daBus : inout std_logic_vector(7
    > downto 0); signal cmd, cs, iowait, rd : out std_logic;);
    >
    > and can I use the clk as it's in a entity? such as clk's events and
    > values. or I can just read the clk value only?


    WAIT is supported in procedures. Also attributes such as 'EVENT can be
    used. That's why you must declare the formal parameter as signal.

    Paul.
     
    Paul Uiterlinden, Apr 13, 2005
    #2
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  3. IcYdRIP

    cristian Guest

    The signals declared in the procedure declaration are local to the
    procedure. So, you can have a clock signal for using within the
    procedure.
    When invoking the procedure you will associate a signal to the
    procedure's clock signal. That associated signal can be the clock that
    you have declared in the entity.
    Since clock is declared as signal you can use all the attributes
    available for signals.

    rgds,

    cristian
     
    cristian, Apr 13, 2005
    #3
  4. cristian wrote:
    > The signals declared in the procedure declaration are local to the
    > procedure. So, you can have a clock signal for using within the
    > procedure.


    A procedure can use a signal passed to it,
    or a signal in the scope of the calling process,
    but if I try to *declare* a signal inside a procedure
    declaration, I will see something like this:

    ** Error: Signal declaration 'bozo' not allowed in this region.

    Signals can be "local" to an architecture, block or package.

    -- Mike Treseler
     
    Mike Treseler, Apr 13, 2005
    #4
  5. IcYdRIP

    IcYdRIP Guest

    thank you !
    since signal declaration is not allowed in the procedure. so the
    signals used in a procedure must be passed from others.

    but I have a doubt. if I invoke a procedure in a process, and the
    process with a clock sensitive signal. since in a process, all sentence
    are executed step by step. when invoking a procedure, the clock signal
    maybe had a stabel value, not in the up edge or down edge. so what
    about the clk's event property? or because the executing time is very
    very short and is always lower than the smallest standard time scale,
    the procedure will still use the event property? or all the property
    will delayed for 1 clock cycle?
    thank you!
     
    IcYdRIP, Apr 14, 2005
    #5
  6. IcYdRIP wrote:
    > thank you !


    You are welcome.

    > but I have a doubt. if I invoke a procedure in a process, and the
    > process with a clock sensitive signal.


    A vhdl procedure is not so complicated.
    It is mainly an editing convenience.
    Get a simulator, try it and see.
    Any invocation of a procedure can be replaced
    by the one or more lines of code that the
    procedure represents.

    See my folder for procedure examples for
    design and simulation.

    http://home.comcast.net/~mike_treseler/


    -- Mike Treseler
     
    Mike Treseler, Apr 14, 2005
    #6
  7. IcYdRIP

    IcYdRIP Guest

    thank you, Mike
    I read and try them first. :)
     
    IcYdRIP, Apr 14, 2005
    #7
  8. IcYdRIP

    cristian Guest

    Mike,
    you are right based on what I wrote, but what I wrote is actually not
    what I mean... :)
    Based on the Procedure definition:
    "Formal parameters are separated by semicolons in the formal parameter
    list. Each formal parameter is essentially a declaration of an
    object that is local to the procedure. "
    I was refering to the formal parameter that may be declared as a
    signal. Therefore, it's local to the procedure. If the formal
    parameter is associated with an 'actual' signal that is a clock signal,
    the clock can be used within the procedure.
    Sorry, about not being clear on my writting.

    rgds,

    cristian
     
    cristian, Apr 15, 2005
    #8
  9. IcYdRIP

    IcYdRIP Guest

    that's ok, cristian. thank you! :)

    and Mike, I've read the uart code.
    It seems all procedures(not in testbench vhdl file) have no parameters.
    and all variables declared in the process are all visible in the
    procedures which are invoked in the process.

    but as book wrote, a procedure doesn't return any result, just change
    the parameter value which will affect the actual parameters when
    invoking. and all variables in a procedure are dynamic, they don't
    store values during two calls. or this rule just affect the variables
    which are declared in the procedure.

    so, as the example uart code wrote, if the variables are declared in
    the process which invokes the procedure, then the procedure can use
    these variables and pass the changed values to the process?

    thank you!
     
    IcYdRIP, Apr 15, 2005
    #9
  10. IcYdRIP wrote:

    > and Mike, I've read the uart code.
    > It seems all procedures(not in testbench vhdl file) have no parameters.


    True. For synthesis, I use procedures to break up
    the pages of sequential code that a single process
    entity requires. Attaching identifiers to blocks of
    code allows me to make the top level procedures
    easier to read. It also allows me to match the
    specific design to the template, that can be used
    for _any_ design.

    > and all variables declared in the process are all visible in the
    > procedures which are invoked in the process.


    Yes. This is the upside for single
    process design entities. No signal
    declarations are required.

    > but as book wrote, a procedure doesn't return any result, just change
    > the parameter value which will affect the actual parameters when
    > invoking. and all variables in a procedure are dynamic, they don't
    > store values during two calls. or this rule just affect the variables
    > which are declared in the procedure.


    Note that the variables *and* the procedures
    are declared between the IS and BEGIN of the single process.
    No variables are declared in the procedures.
    Each process has access can read or write variables
    declared above above.

    This allows code simplification,
    like modifying tx and rx state variables
    in the the cpu_regs procedure.

    > so, as the example uart code wrote, if the variables are declared in
    > the process which invokes the procedure, then the procedure can use
    > these variables and pass the changed values to the process?


    Yes. You've got it.

    -- Mike Treseler
     
    Mike Treseler, Apr 16, 2005
    #10
  11. Re: operation in procedure -- correction

    Correction:

    Wrong:
    "Each process has access can read or write variables
    declared above above."

    Correct:
    Each procedure can read or write variables declared above.


    -- Mike Treseler
     
    Mike Treseler, Apr 16, 2005
    #11
  12. IcYdRIP

    IcYdRIP Guest

    Re: operation in procedure -- correction

    Thank you all, especially Mike!
    I've got it now. :)
     
    IcYdRIP, Apr 16, 2005
    #12
  13. cristian wrote:

    > Based on the Procedure definition:
    > "Formal parameters are separated by semicolons in the formal parameter
    > list. Each formal parameter is essentially a declaration of an
    > object that is local to the procedure. "


    OK, I see what your are saying.
    That definition needs some clarification.
    A formal parameter (say my_arg_s) is just a local alias for
    the actual object that is declared elsewhere in
    the calling process or architecture.
    This is bookkeeping. No new object results.
    I would reword "essentially a declaration".

    > I was refering to the formal parameter that may be declared as a
    > signal.


    This "declaration" is just a hint to the compiler
    that the formal identifier may be treated as
    as signal withing the procedure. I don't understand
    why this "hint" is necessary, but it is for signals.
    Between a procedure's IS and BEGIN I can declare
    temporary constants and variables, but not signals.

    > Therefore, it's local to the procedure.


    The "formal" procedural identifier (say my_arg_s) is local
    to the procedure. The signal itself has architecture
    (or package) scope.

    > If the formal
    > parameter is associated with an 'actual' signal that is a clock signal,
    > the clock can be used within the procedure.


    I agree.

    Note that procedures declared in a process
    already have access to all architecture signals
    and all previously declared process variables.
    No parameters are needed to access these objects.

    A packaged procedure has no scope in the calling
    process, so requires parameters for all
    inputs and outputs.

    -- Mike Treseler
     
    Mike Treseler, Apr 16, 2005
    #13
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