Operator problem VHDL. Beginner

[artvandelay]

Hi! I am rather new to VHDL. I'm getting an error I don't understand why.

This is a part of the code:

  -- state register
  process(clk, reset) 
   begin
    if (reset = '1') then 
	 state <= S0;
	 clkcount <= X"00";
    elsif clk'event and clk = '1' then 
      state <= nextstate;
      clkcount <= clkcount + '1';
    end if;
  end process;

The error is highlighted on the line

clkcount <= clkcount +'1';

and the error is Error (10327): VHDL error at part1.vhd(46): can't determine definition of operator ""+"" -- found 0 possible definitions.

Seems like it doesn't recognize the operator +. This is weird since I've done it like this in an earlier excercise. Any idea why?

 

[StuartHobday]

Add the following to your library declarations

USE ieee.std_logic_unsigned.ALL;