Operator problem VHDL. Beginner

Discussion in 'VHDL' started by artvandelay, Nov 6, 2009.

  1. artvandelay

    artvandelay

    Joined:
    Nov 6, 2009
    Messages:
    3
    Hi! I am rather new to VHDL. I'm getting an error I don't understand why.

    This is a part of the code:

    Code:
      -- state register
      process(clk, reset) 
       begin
        if (reset = '1') then 
    	 state <= S0;
    	 clkcount <= X"00";
        elsif clk'event and clk = '1' then 
          state <= nextstate;
          clkcount <= clkcount + '1';
        end if;
      end process;
    The error is highlighted on the line
    and the error is Error (10327): VHDL error at part1.vhd(46): can't determine definition of operator ""+"" -- found 0 possible definitions.

    Seems like it doesn't recognize the operator +. This is weird since I've done it like this in an earlier excercise. Any idea why?
    artvandelay, Nov 6, 2009
    #1
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  2. artvandelay

    StuartHobday

    Joined:
    Sep 22, 2009
    Messages:
    7
    Location:
    Dorset
    Add the following to your library declarations

    USE ieee.std_logic_unsigned.ALL;
    StuartHobday, Nov 6, 2009
    #2
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