order of array members in vhdl vs edif

Discussion in 'VHDL' started by Vlad Ciubotariu, Feb 15, 2008.

  1. Hi all,

    I have a verification tool that synthesizes vhdl to edf via precision and
    then proceeds from there.

    I realize that for vhdl arrays that are declared from high downto low, the
    corresponding netlist ports appear to be reversed in the netlist.

    The full adders below are correctly cascaded in the netlist. However, the
    bits of a and b are used in the wrong order, e.g. a(0) is fed into the
    second adder, and a(1) into the first.

    Is it the case that a(0) in the netlist means the leftmost member of the
    array? In this case, a(0) in the net would represent a(1) in vhdl?

    thanks for your comments!
    -vlad


    =VHDL code=

    ==Top level entity=

    library IEEE;
    use IEEE.std_logic_1164.all;

    ENTITY adder_bits_n IS
    GENERIC(n: INTEGER := 2);
    PORT (Cin: IN std_logic;
    a, b: IN std_logic_vector(n-1 downto 0);
    S: OUT std_logic_vector(n-1 downto 0);
    Cout: OUT std_logic
    ); END;


    ARCHITECTURE ripple_n_arch OF adder_bits_n IS
    COMPONENT full_adder
    PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic);
    END COMPONENT;
    SIGNAL t: std_logic_vector(n downto 0);
    BEGIN
    t(0) <= Cin; Cout <= t(n);
    FA: for i in 0 to n-1 generate
    FA_i: full_adder PORT MAP (t(i), a(i), b(i), S(i), t(i+1));
    end generate;
    END;

    ==Full Adder==

    library IEEE;
    use IEEE.std_logic_1164.all;

    entity full_adder is
    PORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic);
    end;

    architecture impl of full_adder is
    begin
    Sum <= x xor y xor z;
    Carry <= (x and y) or (x and z) or (y and z);
    end;

    And here's the relevant part of the netlist:

    (cell adder_bits_n (cellType GENERIC)
    (view ripple_n_arch (viewType NETLIST)
    (interface
    (port Cin (direction INPUT))
    (port (array (rename a "a(1:0)") 2 )(direction INPUT))
    (port (array (rename b "b(1:0)") 2 )(direction INPUT))
    (port (array (rename S "S(1:0)") 2 )(direction OUTPUT))
    (port Cout (direction OUTPUT)))
    (property DESIGN_IS_RTL (string "YES"))
    (contents
    (instance FA_0_FA_i (viewRef impl_unfold_1 (cellRef full_adder )))
    (instance FA_1_FA_i (viewRef impl (cellRef full_adder )))
    (net (rename a_1_ "a(1)")
    (joined
    (portRef (member a 0))
    (portRef y (instanceRef FA_1_FA_i ))))
    (net (rename a_0_ "a(0)")
    (joined
    (portRef (member a 1))
    (portRef y (instanceRef FA_0_FA_i ))))
    (net (rename b_1_ "b(1)")
    (joined
    (portRef (member b 0))
    (portRef z (instanceRef FA_1_FA_i ))))
    (net (rename b_0_ "b(0)")
    (joined
    (portRef (member b 1))
    (portRef z (instanceRef FA_0_FA_i ))))
    (net (rename S_1_ "S(1)")
    (joined
    (portRef (member S 0))
    (portRef Sum (instanceRef FA_1_FA_i ))))
    (net (rename S_0_ "S(0)")
    (joined
    (portRef (member S 1))
    (portRef Sum (instanceRef FA_0_FA_i ))))
    (net Cout
    (joined
    (portRef Cout )
    (portRef Carry (instanceRef FA_1_FA_i ))))
    (net (rename t_1_ "t(1)")
    (joined
    (portRef Carry (instanceRef FA_0_FA_i ))
    (portRef x (instanceRef FA_1_FA_i ))))
    (net Cin
    (joined
    (portRef Cin )
    (portRef x (instanceRef FA_0_FA_i ))))))))
    (design adder_bits_n (cellRef adder_bits_n (libraryRef work ))))
     
    Vlad Ciubotariu, Feb 15, 2008
    #1
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  2. On Fri, 15 Feb 2008 09:19:14 -0500, Vlad Ciubotariu <>
    wrote:

    >Hi all,
    >
    >I have a verification tool that synthesizes vhdl to edf via precision and
    >then proceeds from there.
    >
    >I realize that for vhdl arrays that are declared from high downto low, the
    >corresponding netlist ports appear to be reversed in the netlist.

    ....
    > SIGNAL t: std_logic_vector(n downto 0);

    ....
    > FA: for i in 0 to n-1 generate


    What happens if you reverse the generate order to match the input vector bit
    order?

    FA: for i in n-1 downto 0 generate

    - Brian
     
    Brian Drummond, Feb 16, 2008
    #2
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  3. On Sat, 16 Feb 2008 13:18:21 +0000, Brian Drummond wrote:
    >
    > What happens if you reverse the generate order to match the input vector bit
    > order?
    >
    > FA: for i in n-1 downto 0 generate
    >


    diff --suppress-common-lines -y proj_rtl.edf proj_rtl.ed
    (timestamp 2008 02 16 14 57 10) | (timestamp 2008 02 16 14 55 21)
    (instance FA_0_FA_i (viewRef impl_unfold_1 (cellRef ful | (instance FA_1_FA_i (viewRef impl_unfold_1 (cellRef ful
    (instance FA_1_FA_i (viewRef impl (cellRef full_adder ) | (instance FA_0_FA_i (viewRef impl (cellRef full_adder )
    (net Cout | (net Carry

    No substantial changes. The edif and vhdl order matches when the ports are
    declared left to right.

    I currently assume that the vhdl array are represented left to right a =
    <a(left), ..., a(right)> and edif indexes this sequence from 0, left to
    right.

    vlad
     
    Vlad Ciubotariu, Feb 16, 2008
    #3
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