ored bus -- Fatal: (SIGSEGV) Bad handle or reference.

Discussion in 'VHDL' started by Diego UTN-FRP, Jan 6, 2010.

  1. Hello people.

    I am stuck on this error which is not at all descriptive.

    I am using ModelSim PE Student Edition 6.5a.

    I have a bus made of simple bits and bit_vectors.

    The databus is an 8 lines bit bus which should be connected to
    multiple drivers but only one driver will use the bus at the time.
    Thats why i made a resolution function.
    With this resolution function i am able to handle the bus with
    multiple bit_vector drivers. Only one driver will have some lines set
    to one, and when the others are disabled they will be set to null.

    subtype ored_bus_element is bit_vector(RF_BUS_WIDTH-1 downto 0);
    type ored_bus_elements_array is array (natural range <>) of
    ored_bus_element;
    function ored_bus(drivers: ored_bus_elements_array) return
    ored_bus_element;
    subtype ored_bit_bus is ored_bus bit_vector(RF_BUS_WIDTH-1 downto 0);


    function ored_bus(drivers: ored_bus_elements_array) return
    ored_bus_element is
    -- ORed logic will set to logic 1, only when any of the drivers are
    logic 1
    variable accum : ored_bus_element := (others=>'0');
    begin
    for i in drivers'range loop
    for j in 0 to 7 loop
    accum(j) := accum(j) or drivers(i)(j);
    end loop;
    end loop;
    return accum;
    end function;


    Then i have to instantiate my modules (which synthesizes perfectly)
    with this resolution function.


    ad8370: ad8370modul PORT MAP(
    -- WISHBONE SLAVE interface
    wb_clk_i => wb.clk,
    wb_rst_o => wb.rst,
    wb_csel_o => wb.adr,
    wb_dat_o => wb.dat,
    wb_cyc_o => wb.cyc,
    wb_stb_o => wb.stb,
    wb_we_o => wb.we,
    wb_ack_i => wb.ack,
    -- SPI MASTER interface
    spi_interrupt_i => spi_interrupt,
    ad_init_o=> moduls_init(0)
    );

    spimaster: myspi_master PORT MAP(
    -- WISHBONE SLAVE interface
    wb_clk_i => wb.clk,
    wb_rst_i => wb.rst,
    wb_csel_i => wb.adr(0),
    wb_dat_i => wb.dat,
    wb_dat_o => wb.dat,
    wb_cyc_i => wb.cyc,
    wb_stb_i => wb.stb,
    wb_we_i => wb.we,
    wb_ack_o => wb.ack,
    -- SPI MASTER interface
    spi_clk_o => spi_clk,
    spi_master_i => spi_miso,
    spi_master_o => spi_mosi,
    spi_slaveselect_o => spi_slavestart,
    spi_int_o => spi_interrupt
    );
    spislave: myspi_slave PORT MAP(
    -- WISHBONE SLAVE interface
    wb_clk_i => wb.clk,
    wb_rst_i => wb.rst,
    wb_csel_i => wb.adr(1),
    wb_dat_i => wb.dat,
    wb_dat_o => wb.dat,
    wb_cyc_i => wb.cyc,
    wb_stb_i => wb.stb,
    wb_we_i => wb.we,
    wb_ack_o => wb.ack,
    -- SPI SLAVE interface
    spi_clk_i => spi_clk,
    spi_slave_i => spi_mosi,
    spi_slave_o => spi_miso,
    spi_slaveselect_i => spi_slavestart,
    spi_int_o => open
    );

    Note that i read and write to the same line:
    wb_dat_i => wb.dat,
    wb_dat_o => wb.dat,

    What i need is to read in each modul from the resultant bus and use OR
    gate to write to the bus.

    Any way, i am not sure why, but it says always:

    Fatal: (SIGSEGV) Bad handle or reference.

    So i think that it has problems to do this in this way.

    I tried in another way, without resolution functions.
    And using a process to calculate the ORed bus and different signals
    connected in the ouput and input pins, and it worked, but it requires
    more code and then the existence of resolution functions is sinnlos.

    What do you think?
    I am doing something wrong with this resolution functions?
     
    Diego UTN-FRP, Jan 6, 2010
    #1
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  2. Diego UTN-FRP

    HT-Lab Guest

    HT-Lab, Jan 6, 2010
    #2
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