[OT] Makefile

Discussion in 'C Programming' started by riccardo, Sep 1, 2010.

  1. riccardo

    riccardo Guest

    Hi list,
    sorry for being OT. I have troubles with dependencies in a Makefile;

    I have a series of $FILENAME.c $FILENAME.h files but also some other
    SOMEOTHERFILENAME.h header files wich $FILENAME.c depend upon.

    I'm using the line

    ..c.o:
    $(GCC) ...

    which doesn't seem to accept dependecies statements, therefore the
    following doesn't bring any change

    ..c.o: $SOMEOTHERFILENAME.h
    $(GCC) ...

    The correct way could be to specify deps for each .c file separately:

    $FILENAME1.c: $FILENAME1.h $SOMEOTHERFILENAME.h
    $(GCC) ...

    Is there a more compact and jet portable way of doing this?
    Thankx and sorry again for being ot!
    R
     
    riccardo, Sep 1, 2010
    #1
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  2. riccardo

    Rui Maciel Guest

    riccardo wrote:

    > Hi list,
    > sorry for being OT. I have troubles with dependencies in a Makefile;
    >
    > I have a series of $FILENAME.c $FILENAME.h files but also some other
    > SOMEOTHERFILENAME.h header files wich $FILENAME.c depend upon.
    >
    > I'm using the line
    >
    > .c.o:
    > $(GCC) ...
    >
    > which doesn't seem to accept dependecies statements, therefore the
    > following doesn't bring any change
    >
    > .c.o: $SOMEOTHERFILENAME.h
    > $(GCC) ...
    >
    > The correct way could be to specify deps for each .c file separately:
    >
    > $FILENAME1.c: $FILENAME1.h $SOMEOTHERFILENAME.h
    > $(GCC) ...
    >
    > Is there a more compact and jet portable way of doing this?



    It is possible to use implicit rules and still set individual dependencies on specific target
    files covered by the specific rules. To be able to do that you only need to add extra
    prerequisites to your files. So, for example, you can simply do the following:


    <code>
    ..c.o:
    $(GCC) ...

    $FILENAME1.c: $FILENAME1.h $SOMEOTHERFILENAME.h
    </code>


    For more information on how to write Makefile rules you can check out Make's manual at:

    http://www.gnu.org/software/make/manual/make.html


    Hope this helps,
    Rui Maciel
     
    Rui Maciel, Sep 1, 2010
    #2
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  3. riccardo

    riccardo Guest


    > <code>
    > .c.o:
    > $(GCC) ...
    >
    > $FILENAME1.c: $FILENAME1.h $SOMEOTHERFILENAME.h
    > </code>
    >


    Apparently it's not helping:

    <code>
    OBJFILES=foo.c main.c

    all: $(OBJFILES)

    ..c.o:
    $(GCC) $(CFLAGS) $(DEFINES) $(INCLUDES) $< -o $@

    foo.c: foo.h myheader.h
    </code>

    Adding the above last line and changing myheader.h doesn't force foo.c
    recompiling (GNU Make 3.81).
    R
     
    riccardo, Sep 1, 2010
    #3
  4. riccardo

    riccardo Guest

    riccardo, Sep 1, 2010
    #4
  5. riccardo

    Jorgen Grahn Guest

    On Wed, 2010-09-01, riccardo wrote:
    > Hi list,
    > sorry for being OT. I have troubles with dependencies in a Makefile;
    >
    > I have a series of $FILENAME.c $FILENAME.h files but also some other
    > SOMEOTHERFILENAME.h header files wich $FILENAME.c depend upon.
    >
    > I'm using the line
    >
    > .c.o:
    > $(GCC) ...


    With a modern make you never have to tell it stuff like that.
    Gnu make already knows that foo.o is created from foo.c
    using $(CC) $(CFLAGS) $(CPPFLAGS) ... or whatever it is (see the
    manual).

    You just have to specify dependencies on header files

    foo.o: foo.h bar.h

    and what should go in CFLAGS and CPPFLAGS (and in CC, if you're on a
    system where make may not default to using gcc).

    /Jorgen

    --
    // Jorgen Grahn <grahn@ Oo o. . .
    \X/ snipabacken.se> O o .
     
    Jorgen Grahn, Sep 1, 2010
    #5
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