<OT?> nonstandard use

Discussion in 'VHDL' started by churchy, Sep 21, 2011.

  1. churchy

    churchy Guest

    Is it reasonable to use the gates in CPLD/FPGA "gates" in a nonstandard
    "semi-analog" manner? Doing things like using a gate as a comparator etc.

    For example, can leftover gates in a device be used to clock the device
    with something like the classic 2 not, 2 resistor & a cap oscillator?

    CPLDs are nominally still gates but it seem like FPGA might get a little
    weird with this though basically externally both ae supposed to look like
    simple logic.

    3ch
    churchy, Sep 21, 2011
    #1
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  2. On 2011-09-21, churchy <> wrote:
    > Is it reasonable to use the gates in CPLD/FPGA "gates" in a nonstandard
    > "semi-analog" manner? Doing things like using a gate as a comparator etc.
    >

    I wouldn't recommend it, but you can certainly do something like this. You
    can certainly implement something like a ring oscillator in an FPGA if you
    felt like it.

    One of the neatest ways to abuse an FPGA to do analog processin that I've seen
    can be seen on bunnie's blog at http://www.bunniestudios.com/wordpress/?page_id=22
    and http://www.bunniestudios.com/blog/?page_id=24 (a way to create a DAC using
    just an FPGA and some resistors).

    And another favourite: http://www.informatics.sussex.ac.uk/users/adrianth/cacm99/node3.html
    http://www.informatics.sussex.ac.uk/users/adrianth/ascot/paper/paper.html


    /Andreas
    Andreas Ehliar, Sep 21, 2011
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  3. churchy

    Jezmo Guest

    On Sep 21, 7:41 pm, churchy <> wrote:
    > Is it reasonable to use the gates in CPLD/FPGA "gates" in a nonstandard
    > "semi-analog" manner? Doing things like using a gate as a comparator etc.
    >
    > For example, can leftover gates in a device be used to clock the device
    > with something like the classic 2 not, 2 resistor & a cap oscillator?
    >
    > CPLDs are nominally still gates but it seem like FPGA might get a little
    > weird with this though basically externally both ae supposed to look like
    > simple logic.
    >
    >    3ch


    It is possible with CPLDs and I have done it myself, I doubt that it
    would work with FPGAs due to the complex nature of the output drivers.
    Jezmo, Sep 24, 2011
    #3
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